Research Output 1973 2019

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Conference article
2009
1 Citation (Scopus)
Arrival Time
Power Consumption
Electric power utilization
Chip
Error analysis
2003

Routing methodology for minimizing interconnect energy dissipation

Sakai, A., Yamada, T., Matsushita, Y. & Yasuura, H., Jul 28 2003, In : Proceedings of the IEEE Great Lakes Symposium on VLSI. p. 120-123 4 p.

Research output: Contribution to journalConference article

Energy dissipation
Crosstalk
Image processing
Networks (circuits)
Costs
2002
2 Citations (Scopus)

An accelerated datapath width optimization scheme for area reduction of embedded systems

Uddin, M. M., Cao, Y. & Yasuura, H., Dec 1 2002, In : Proceedings of the International Symposium on System Synthesis. p. 32-37 6 p.

Research output: Contribution to journalConference article

Embedded systems
25 Citations (Scopus)

Data memory design considering effective bitwidth for low-energy embedded systems

Cao, Y., Tomiyama, H., Okuma, T. & Yasuura, H., Dec 1 2002, In : Proceedings of the International Symposium on System Synthesis. p. 201-206 6 p.

Research output: Contribution to journalConference article

Embedded systems
Data storage equipment
Random access storage
2000
115 Citations (Scopus)

A bus delay reduction technique considering crosstalk

Hirose, K. & Yasuura, H., Dec 1 2000, In : Proceedings -Design, Automation and Test in Europe, DATE. p. 441-445 5 p., 840308.

Research output: Contribution to journalConference article

Crosstalk
Wire
Telecommunication repeaters
SPICE
Capacitance
37 Citations (Scopus)

Analysis and minimization of test time in a combined BIST and external test approach

Sugihara, M., Date, H. & Yasuura, H., Dec 1 2000, In : Proceedings -Design, Automation and Test in Europe, DATE. p. 134-140 7 p., 840029.

Research output: Contribution to journalConference article

Built-in self test
Testing
30 Citations (Scopus)

A power reduction technique with object code merging for application specific embedded processors

Ishihara, T. & Yasuura, H., Dec 1 2000, In : Proceedings -Design, Automation and Test in Europe, DATE. p. 617-623 7 p., 840849.

Research output: Contribution to journalConference article

Merging
ROM
Decoding
Data storage equipment
Experiments
1998
24 Citations (Scopus)

Instruction scheduling for power reduction in processor-based system design

Tomiyama, H., Ishihara, T., Inoue, A. & Yasuura, H., Dec 1 1998, In : Proceedings -Design, Automation and Test in Europe, DATE. p. 855-860 6 p., 655958.

Research output: Contribution to journalConference article

Systems analysis
Scheduling
Scheduling algorithms
Data storage equipment
1997
16 Citations (Scopus)

Memory-CPU size optimization for embedded system designs

Shackleford, B., Yasuda, M., Okushi, E., Koizumi, H., Tomiyama, H. & Yasuura, H., Jan 1 1997, In : Proceedings - Design Automation Conference. p. 246-251 6 p.

Research output: Contribution to journalConference article

Computer peripheral equipment
Cost reduction
Application programs
Embedded systems
Computer hardware
1996
23 Citations (Scopus)

Optimal code placement of embedded software for instruction caches

Tomiyama, H. & Yasuura, H., Jan 1 1996, In : Proceedings of European Design and Test Conference. p. 96-101 6 p.

Research output: Contribution to journalConference article

Embedded software
Linear programming
7 Citations (Scopus)

Size-constrained code placement for cache miss rate reduction

Tomiyama, H. & Yasuura, H., Dec 1 1996, In : Proceedings of the International Symposium on System Synthesis. p. 96-101 6 p.

Research output: Contribution to journalConference article

Embedded systems
Electric power utilization