Research Output per year
Research Output 1978 2017
- 1 - 50 out of 174 results
- Title (ascending)
2004 2nd workshop on embedded systems for real-time multimedia (ESTIMedia 2004)
Marculescu, R., Miranda, M., Fohler, G., Yasuura, H. & Hu, S., 2004, Proceedings of the 2004 2nd Workshop on Embedded Systems for Real-Time Multimedia. Miranda, M. & Marculescu, R. (eds.).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Embedded systems
6
Citations
(Scopus)
A bus delay reduction technique considering crosstalk
Hirose, K. & Yasuura, H., Jan 10 2002, In : Electronics and Communications in Japan, Part III: Fundamental Electronic Science (English translation of Denshi Tsushin Gakkai Ronbunshi). 85, 1, p. 24-31 8 p.Research output: Contribution to journal › Article
Crosstalk
Wire
Telecommunication repeaters
SPICE
Switches
115
Citations
(Scopus)
A bus delay reduction technique considering crosstalk
Hirose, K. & Yasuura, H., Dec 1 2000, In : Proceedings -Design, Automation and Test in Europe, DATE. p. 441-445 5 p., 840308.Research output: Contribution to journal › Conference article
Crosstalk
Wire
Telecommunication repeaters
SPICE
Capacitance
12
Citations
(Scopus)
A case study of Short Term Cell-Flipping technique for mitigating NBTI degradation on cache
Kunitake, Y., Sato, T. & Yasuura, H., 2010, Proceedings of the 2nd Asia Symposium on Quality Electronic Design, ASQED 2010. p. 301-307 7 p. 5548256Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Static random access storage
Transistors
Degradation
Threshold voltage
Cache memory
8
Citations
(Scopus)
A design for a low-power digital matched filter applicable to W-CDMA
Goto, S., Yamada, T., Takayama, N., Yasuura, H., Matsushita, Y. & Harada, Y., Jan 1 2002, Proceedings - Euromicro Symposium on Digital System Design: Architectures, Methods and Tools, DSD 2002. Edwards, M. (ed.). Institute of Electrical and Electronics Engineers Inc., p. 210-217 8 p. 1115371. (Proceedings - Euromicro Symposium on Digital System Design: Architectures, Methods and Tools, DSD 2002).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Matched filters
Digital filters
Code division multiple access
Electric power utilization
Flip flop circuits
7
Citations
(Scopus)
A design method for a low power equalization circuit by adaptive bitwidth control
Tarumi, K., Muroyama, M., Yamaguchi, S. & Yasuura, H., 2004, Proceedings - IEEE International Symposium on Communications and Information Technologies, ISCIT 2004. Vol. 2. p. 704-709 6 p.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Networks (circuits)
A door access control system with mobile phones
Yamasaki, T., Nakamura, T., Baba, K. & Yasuura, H., Dec 3 2007, Personal Wireless Communications: The 12th IFIP International Conference on Personal Wireless Communications (PWC 2007), Prague, Czech Republic, September 2007. Bestak, R., Simak, B. & Kozlowska, E. (eds.). p. 230-240 11 p. (IFIP International Federation for Information Processing; vol. 245).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Access control
Mobile phone
Delegation
A framework of authentic post-issuance program modification for multi-application smart cards
Uddin, M. M., Zabir, S. M. S., Nohara, Y. & Yasuura, H., Dec 1 2008, Proceedings of the 2008 International Conference on Wireless Networks, ICWN 2008. p. 288-294 7 p. (Proceedings of the 2008 International Conference on Wireless Networks, ICWN 2008).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Smart cards
Hash functions
Function generators
Authentication
Costs
1
Citation
(Scopus)
A low complexity and energy efficient dynamic channel allocation algorithm for multiuser OFDM
EL Bourichi, A. & Yasuura, H., 2007, 2007 Wireless Telecommunications Symposium, WTS 2007. 4563310Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Adaptive modulation
Orthogonal frequency division multiplexing
Base stations
energy
Resource allocation
6
Citations
(Scopus)
A low-power digital matched filter for spread-spectrum systems
Goto, S., Yamada, T., Takayama, N., Matsushita, Y., Harada, Y. & Yasuura, H., Dec 1 2002, p. 301-306. 6 p.Research output: Contribution to conference › Paper
Matched filters
Digital filters
Electric power utilization
Communication systems
Capacitance
1
Citation
(Scopus)
A memory power optimization technique for application specific embedded systems
Ishihara, T. & Yasuura, H., Jan 1 1999, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E82-A, 11, p. 2366-2374 9 p.Research output: Contribution to journal › Article
Embedded systems
Embedded Systems
Optimization Techniques
Data storage equipment
ROM
1
Citation
(Scopus)
A micro-vectorprocessor Architecture - Performance Modeling and Benchmarking -
Hashimoto, T., Hironaka, T., Murakami, K. & Yasuura, H., Aug 1 1993, Proceedings of the 7th International Conference on Supercomputing, ICS 1993. Association for Computing Machinery, p. 308-317 10 p. (Proceedings of the International Conference on Supercomputing; vol. Part F129670).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Benchmarking
Bandwidth
Data storage equipment
2
Citations
(Scopus)
A module generator of 2-level neuron MOS circuits
Ike, K., Hirose, K. & Yasuura, H., Jan 1 1998, In : Computers and Electrical Engineering. 24, 1-2, p. 33-41 9 p.Research output: Contribution to journal › Article
Neurons
Networks (circuits)
MOSFET devices
Transistors
1
Citation
(Scopus)
A multi-application smart card system with authentic post-issuance program modification
Uddin, M. M., Nohara, Y., Ikeda, D. & Yasuura, H., Jan 1 2008, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E91-A, 1, p. 229-235 7 p.Research output: Contribution to journal › Article
Smart cards
Smart Card
One-way Hash Function
Function generators
Pseudorandom number Generator
2
Citations
(Scopus)
An accelerated datapath width optimization scheme for area reduction of embedded systems
Uddin, M. M., Cao, Y. & Yasuura, H., Dec 1 2002, In : Proceedings of the International Symposium on System Synthesis. p. 32-37 6 p.Research output: Contribution to journal › Conference article
Embedded systems
37
Citations
(Scopus)
Analysis and minimization of test time in a combined BIST and external test approach
Sugihara, M., Date, H. & Yasuura, H., Dec 1 2000, In : Proceedings -Design, Automation and Test in Europe, DATE. p. 134-140 7 p., 840029.Research output: Contribution to journal › Conference article
Built-in self test
Testing
1
Citation
(Scopus)
Analysis of effects of input arrival time variations on on-chip bus power consumption
Muroyama, M., Ishihara, T. & Yasuura, H., Mar 11 2009, In : Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 5349 LNCS, p. 62-71 10 p.Research output: Contribution to journal › Conference article
Arrival Time
Power Consumption
Electric power utilization
Chip
Error analysis
An anonymous authentication protocol with single-database PIR
Nakamura, T., Inenaga, S., Baba, K., Ikeda, D. & Yasuura, H., Dec 1 2011, Information Security 2011 - Proceedings of the Ninth Australasian Information Security Conference, AISC 2011. p. 3-8 6 p. (Conferences in Research and Practice in Information Technology Series; vol. 116).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Authentication
Managers
Communication
8
Citations
(Scopus)
An energy characterization framework for software-based embedded systems
Lee, D., Ishihara, T., Muroyama, M., Yasuura, H. & Fallah, F., Dec 1 2006, Proceedings of the 2006 IEEE/ACM/IFIP Workshop on Embedded Systems for Real Time Multimedia, ESTIMEDIA 2006. p. 59-64 6 p. 4115455Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Embedded systems
Energy utilization
Application programs
Linear programming
Microprocessor chips
An estimation of encryption LSI testability against scan-based attack
Yoshimura, M., Ito, Y. & Yasuura, H., Dec 1 2010, ISCIT 2010 - 2010 10th International Symposium on Communications and Information Technologies. p. 727-731 5 p. 5665083. (ISCIT 2010 - 2010 10th International Symposium on Communications and Information Technologies).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Cryptography
Observability
Controllability
A new VLSI algorithm for high throughput image filtering
Islam, F. F., Yasuura, H. & Tamaru, K., Jan 1 1992, 1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992. Institute of Electrical and Electronics Engineers Inc., p. 2441-2444 4 p. 230523. (Proceedings - IEEE International Symposium on Circuits and Systems; vol. 5).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Throughput
Masks
Pixels
Logic gates
An identifiable yet unlinkable authentication system with smart cards for multiple services
Nakamura, T., Inenaga, S., Ikeda, D., Baba, K. & Yasuura, H., May 20 2010, Computational Science and Its Applications - ICCSA 2010 - International Conference, Proceedings. PART 4 ed. p. 236-251 16 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 6019 LNCS, no. PART 4).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Smart cards
Smart Card
Authentication
Data storage equipment
Hash functions
3
Citations
(Scopus)
An information platform for low-literate villagers
Ahmed, A. U., Kabir, L. & Yasuura, H., Jul 12 2010, 24th IEEE International Conference on Advanced Information Networking and Applications, AINA 2010. p. 1271-1277 7 p. 5474860. (Proceedings - International Conference on Advanced Information Networking and Applications, AINA).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Internet
Economics
2
Citations
(Scopus)
An interactive simulation system for structured logic design - ISS
Sakai, T., Tsuchida, Y., Yasuura, H., Ooi, Y., Ono, Y., Kano, H., Kimura, S. & Yajima, S., Jan 1 1982, In : Proceedings - Design Automation Conference. p. 747-754 8 p.Research output: Contribution to journal › Conference article
Logic Design
Interactive Simulation
Logic design
Interactive Systems
Simulation System
4
Citations
(Scopus)
Anonymous authentication systems based on private information retrieval
Nakamura, T., Inenaga, S., Ikeda, D., Baba, K. & Yasuura, H., 2009, 2009 1st International Conference on Networked Digital Technologies, NDT 2009. p. 53-58 6 p. 5272083Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Information retrieval
Authentication
Network protocols
Servers
1
Citation
(Scopus)
An optimization technique for low-energy embedded memory systems
Matsumura, T., Ishihara, T. & Yasuura, H., Dec 1 2009, In : IPSJ Transactions on System LSI Design Methodology. 2, p. 239-249 11 p.Research output: Contribution to journal › Article
Computer systems
Data storage equipment
Energy utilization
Memory architecture
Static random access storage
A note on biometrics-based authentication with portable device
Ohtsuka, S., Kawamoto, S., Takano, S., Baba, K. & Yasuura, H., 2008, SECRYPT 2008 - International Conference on Security and Cryptography, Proceedings. p. 99-102 4 p.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Biometrics
Authentication
Mobile phones
Servers
6
Citations
(Scopus)
An RFID-based multi-service system for supporting conference events
Watanabef, T., Inoue, S., Yasuura, H., Sasaki, J., Aoki, Y. & Akimoto, K., Dec 1 2005, Proceedings of the 2005 International Conference on Active Media Technology, AMT 2005. p. 435-439 5 p. 1505390. (Proceedings of the 2005 International Conference on Active Media Technology, AMT 2005; vol. 2005).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Radio frequency identification (RFID)
Nameplates
Experiments
10
Citations
(Scopus)
An RTOS in hardware for energy efficient software-based TCP/IP processing
Maruyama, N., Ishihara, T. & Yasuura, H., Aug 24 2010, Proceedings of the 2010 IEEE 8th Symposium on Application Specific Processors, SASP'10. p. 58-63 6 p. 5521147. (Proceedings of the 2010 IEEE 8th Symposium on Application Specific Processors, SASP'10).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Computer hardware
Hardware
Processing
Energy efficiency
Firmware
2
Citations
(Scopus)
A power reduction scheme for data buses by dynamic detection of active bits
Muroyama, M., Hyodo, A., Okuma, T. & Yasuura, H., Apr 2004, In : IEICE Transactions on Electronics. E87-C, 4, p. 598-605 8 p.Research output: Contribution to journal › Article
Electric power utilization
2
Citations
(Scopus)
A power reduction scheme for data buses by dynamic detection of active bits
Muroyama, M., Hyodo, A., Okuma, T. & Yasuura, H., Jan 1 2003, Proceedings - Euromicro Symposium on Digital System Design, DSD 2003. Institute of Electrical and Electronics Engineers Inc., p. 408-415 8 p. (Proceedings - Euromicro Symposium on Digital System Design, DSD 2003).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Electric power utilization
30
Citations
(Scopus)
A power reduction technique with object code merging for application specific embedded processors
Ishihara, T. & Yasuura, H., Dec 1 2000, In : Proceedings -Design, Automation and Test in Europe, DATE. p. 617-623 7 p., 840849.Research output: Contribution to journal › Conference article
Merging
ROM
Decoding
Data storage equipment
Experiments
A proposal of secure information infrastructure based on PID
Hamasaki, Y. & Yasuura, H., Sep 1 2002, In : Research Reports on Information Science and Electrical Engineering of Kyushu University. 7, 2, p. 139-148 10 p.Research output: Contribution to journal › Article
8
Citations
(Scopus)
A replacement strategy for canary Flip-Flops
Kunitake, Y., Sato, T. & Yasuura, H., Dec 1 2010, Proceedings - 16th IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2010. p. 227-228 2 p. 5703250. (Proceedings - 16th IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2010).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Flip flop circuits
Electric power utilization
Semiconductor materials
Networks (circuits)
8
Citations
(Scopus)
A secure high-speed identification scheme for RFID using Bloom filters
Nohara, Y., Inoue, S. & Yasuura, H., Aug 14 2008, ARES 2008 - 3rd International Conference on Availability, Security, and Reliability, Proceedings. p. 717-722 6 p. 4529413. (ARES 2008 - 3rd International Conference on Availability, Security, and Reliability, Proceedings).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Radio frequency identification (RFID)
Identification (control systems)
Data storage equipment
Ubiquitous computing
Data structures
2
Citations
(Scopus)
A selective replacement method for timing-error-predicting flip-flops
Kunitake, Y., Sato, T., Yasuura, H. & Hayashida, T., Oct 13 2011, 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011. 6026267. (Midwest Symposium on Circuits and Systems).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Flip flop circuits
Redundancy
Transistors
Networks (circuits)
A selective replacement method for timing-error-predicting flip-flops
Kunitake, Y., Sato, T., Yasuura, H. & Hayashida, T., Oct 1 2012, In : Journal of Circuits, Systems and Computers. 21, 6, 1240013.Research output: Contribution to journal › Article
Flip flop circuits
Redundancy
Electric power utilization
Electric potential
Transistors
1
Citation
(Scopus)
A single cycle accessible two-level cache architecture for the energy consumption of embedded systems
Yamaguchi, S., Ishihara, T. & Yasuura, H., Dec 1 2008, 2008 International SoC Design Conference, ISOCC 2008. 4815604. (2008 International SoC Design Conference, ISOCC 2008; vol. 1).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Embedded systems
Energy utilization
Data storage equipment
Degradation
Experiments
1
Citation
(Scopus)
A software technique to improve lifetime of caches containing ultra-leaky SRAM cells caused by within-die Vth variation
Goudarzi, M., Ishihara, T. & Yasuura, H., Dec 1 2008, In : Microelectronics Journal. 39, 12, p. 1797-1808 12 p.Research output: Contribution to journal › Article
Static random access storage
Transistors
transistors
computer programs
life (durability)
3
Citations
(Scopus)
A software technique to improve yield of processor chips in presence of ultra-leaky SRAM cells caused by process variation
Goudarzi, M., Ishihara, T. & Yasuura, H., Dec 1 2007, Proceedings of the ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007. p. 878-883 6 p. 4196146. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Static random access storage
Transistors
Threshold voltage
Redundancy
Energy conservation
6
Citations
(Scopus)
A systematic approach for the reliability of RFID systems
Inoue, S., Hagiwara, D. & Yasuura, H., Dec 1 2004.Research output: Contribution to conference › Paper
Radio frequency identification (RFID)
23
Citations
(Scopus)
A system-level energy minimization approach using datapath width optimization
Cao, Y. & Yasuura, H., Jan 1 2001, p. 231-236. 6 p.Research output: Contribution to conference › Paper
Electron energy levels
Application programs
Energy conservation
Energy utilization
Experiments
7
Citations
(Scopus)
A test methodology for core-based system lsis
Sugihara, M., Date, H. & Yasuura, H., Jan 1 1998, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E81-A, 12, p. 2640-2645 6 p.Research output: Contribution to journal › Article
Built-in self test
Methodology
Testing
Built-in Self-test
Combinatorial optimization
Automatic generation of command level simulation model of a processor from RT level description
Akaboshi, H. & Yasuura, H., May 1 1996, In : Electronics and Communications in Japan, Part III: Fundamental Electronic Science (English translation of Denshi Tsushin Gakkai Ronbunshi). 79, 5, p. 35-45 11 p.Research output: Contribution to journal › Article
Plant layout
Digital circuits
Microprocessor chips
Logic Synthesis
2
Citations
(Scopus)
A variation-aware low-power coding methodology for tightly coupled buses
Muroyama, M., Tarumi, K., Makiyama, K. & Yasuura, H., Dec 1 2005, Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005. p. 557-560 4 p. 1466226. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; vol. 1).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Electric power utilization
Capacitance
System-on-chip
1
Citation
(Scopus)
Basic experimentation on accuracy of power estimation for CMOS VLSI circuits
Ishihara, T. & Yasuura, H., Jan 1 1996, p. 117-120. 4 p.Research output: Contribution to conference › Paper
VLSI circuits
Energy dissipation
Electric power utilization
Microprocessor chips
Clocks
Basic experimentation on accuracy of power estimation for CMOS VLSI circuits
Ishihara, T. & Yasuura, H., Dec 1 1996, p. 117-120. 4 p.Research output: Contribution to conference › Paper
VLSI circuits
Energy dissipation
Electric power utilization
Microprocessor chips
Clocks
Behavioral verification of cpus using functional information extraction
Ohmura, M., Tamaru, K. & Yasuura, H., Jan 1 1994, In : Electronics and Communications in Japan (Part III: Fundamental Electronic Science). 77, 3, p. 52-61 10 p.Research output: Contribution to journal › Article
Program processors
Networks (circuits)
Logic circuits
Microprocessor chips
Computer aided design
4
Citations
(Scopus)
Bit-parallel block-parallel functional memory type parallel processor architecture
Kobayashi, K., Tamaru, K., Yasuura, H. & Onodera, H., Jul 1 1993, In : IEICE Transactions on Electronics. E76-C, 7, p. 1151-1158 8 p.Research output: Contribution to journal › Article
Data storage equipment
Parallel architectures
Associative storage
Bitwidth optimization for low power digital FIR filter design
Tarumi, K., Hyodo, A., Muroyama, M. & Yasuura, H., Jan 1 2005, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E88-A, 4, p. 869-875 7 p.Research output: Contribution to journal › Article
FIR Filter
Digital Filter
Filter Design
FIR filters
Digital filters