• 1887 Citations
  • 19 h-Index
1978 …2017
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Research Output 1978 2017

2000
37 Citations (Scopus)

Analysis and minimization of test time in a combined BIST and external test approach

Sugihara, M., Date, H. & Yasuura, H., Dec 1 2000, In : Proceedings -Design, Automation and Test in Europe, DATE. p. 134-140 7 p., 840029.

Research output: Contribution to journalConference article

Built-in self test
Testing
30 Citations (Scopus)

A power reduction technique with object code merging for application specific embedded processors

Ishihara, T. & Yasuura, H., Dec 1 2000, In : Proceedings -Design, Automation and Test in Europe, DATE. p. 617-623 7 p., 840849.

Research output: Contribution to journalConference article

Merging
ROM
Decoding
Data storage equipment
Experiments
2 Citations (Scopus)

Flexible system LSI for embedded systems and its optimization techniques

Inoue, A., Ishihara, T. & Yasuura, H., Jun 1 2000, In : Design Automation for Embedded Systems. 5, 2, p. 179-205 27 p.

Research output: Contribution to journalArticle

Embedded systems
Costs
Masks
Fabrication
Electric power utilization
2 Citations (Scopus)

Functional redundancy for dynamic exploitation of performance-energy consumption trade-offs

Goulart Ferreira, V. M. & Yasuura, H., Jan 1 2000, Proceedings - 13th Symposium on Integrated Circuits and Systems Design. Reis, R., Van Noije, W. & Monteiro, J. C. (eds.). Institute of Electrical and Electronics Engineers Inc., p. 165-170 6 p. 876025. (Proceedings - 13th Symposium on Integrated Circuits and Systems Design).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Redundancy
Energy utilization
Networks (circuits)
Electric power utilization
Systems analysis

One language or more? How can we design an SoC at a system level?

Imai, M., Smith, G., Schulz, S., Bartleson, K., Gajski, D. D., Rosenstiel, W., Flake, P. & Yasuura, H., Dec 1 2000, Proceedings of the 2000 Asia and South Pacific Design Automation Conference, ASP-DAC 2000. p. 653-654 2 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

System-on-chip

Synthesis of minimum-cost multilevel logic networks via genetic algorithm

Shackleford, B., Okushi, E., Yasuda, M., Koizuml, H., Seo, K. & Yasuura, H., Jan 1 2000, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E83-A, 12, p. 2528-2536 9 p.

Research output: Contribution to journalArticle

Network Algorithms
Genetic algorithms
Genetic Algorithm
Synthesis
Logic
4 Citations (Scopus)

System LSI design methods for low power LSIs

Yasuura, H. & Ishihara, T., Jan 1 2000, In : IEICE Transactions on Electronics. E83-C, 2, p. 143-152 10 p.

Research output: Contribution to journalArticle

Systems analysis
1999
1 Citation (Scopus)
Embedded systems
Embedded Systems
Optimization Techniques
Data storage equipment
ROM

Educational results of hardware course with FPGAs

Sawada, S., Tomiyasu, H. & Yasuura, H., Mar 1 1999, In : Research Reports on Information Science and Electrical Engineering of Kyushu University. 4, 1, p. 87-92 6 p.

Research output: Contribution to journalArticle

Field programmable gate arrays (FPGA)
Students
Hardware
Microprocessor chips
Control facilities
59 Citations (Scopus)

Real-Time Task Scheduling for a Variable Voltage Processor

Okuma, T., Ishihara, T. & Yasuura, H., Nov 1 1999, Proceedings of the 12th International Symposium on System Synthesis, ISSS 1999. IEEE Computer Society, (Proceedings of the International Symposium on System Synthesis; vol. Part F129194).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Scheduling
Electric potential
Program processors
Energy utilization
1998
2 Citations (Scopus)

A module generator of 2-level neuron MOS circuits

Ike, K., Hirose, K. & Yasuura, H., Jan 1 1998, In : Computers and Electrical Engineering. 24, 1-2, p. 33-41 9 p.

Research output: Contribution to journalArticle

Neurons
Networks (circuits)
MOSFET devices
Transistors
7 Citations (Scopus)

A test methodology for core-based system lsis

Sugihara, M., Date, H. & Yasuura, H., Jan 1 1998, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E81-A, 12, p. 2640-2645 6 p.

Research output: Contribution to journalArticle

Built-in self test
Methodology
Testing
Built-in Self-test
Combinatorial optimization
14 Citations (Scopus)

Embedded system design using soft-core processor and Valen-C

Yasuura, H., Tomiyama, H., Inoue, A. & Eko Fajar, N., Sep 1998, In : Journal of Information Science and Engineering. 14, 3, p. 587-603 17 p.

Research output: Contribution to journalArticle

Embedded systems
Systems analysis
ROM
Random access storage
programming language

High-efficiency RF suppression circuit for fluorescent lamp inverters using charge pump and partial smoothing capacitors

Suzuki, F., Okino, K., Nishimura, Y., Yamazaki, H., Koizumi, H. & Yasuura, H., Jan 1 1998, PESC Record - IEEE Annual Power Electronics Specialists Conference. Anon (ed.). p. 1733-1738 6 p. (PESC Record - IEEE Annual Power Electronics Specialists Conference; vol. 2).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Fluorescent lamps
Capacitors
Pumps
Networks (circuits)
Electric lamps
14 Citations (Scopus)

Instruction encoding techniques for area minimization of instruction ROM

Okuma, T., Tomiyama, H., Inoue, A., Fajar, E. & Yasuura, H., Dec 2 1998, Proceedings of the 11th International Symposium on System Synthesis, ISSS 1998. Catthoor, F. (ed.). IEEE Computer Society, p. 125-130 6 p. (Proceedings of the International Symposium on System Synthesis; vol. Part F129250).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

ROM
Embedded systems
Systems analysis
Data storage equipment
24 Citations (Scopus)

Instruction scheduling for power reduction in processor-based system design

Tomiyama, H., Ishihara, T., Inoue, A. & Yasuura, H., Dec 1 1998, In : Proceedings -Design, Automation and Test in Europe, DATE. p. 855-860 6 p., 655958.

Research output: Contribution to journalConference article

Systems analysis
Scheduling
Scheduling algorithms
Data storage equipment
5 Citations (Scopus)

Instruction scheduling to reduce switching activity of off-chip buses for low-power systems with caches

Tomiyama, H., Ishihara, T., Inoue, A. & Yasuura, H., Jan 1 1998, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E81-A, 12, p. 2621-2629 9 p.

Research output: Contribution to journalArticle

Instruction Scheduling
Power System
Cache
Chip
Capacitance
23 Citations (Scopus)

Language and compiler for optimizing datapath widths of embedded systems

Inoue, A., Tomiyama, H., Okuma, T., Kanbara, H. & Yasuura, H., Jan 1 1998, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E81-A, 12, p. 2595-2604 10 p.

Research output: Contribution to journalArticle

Embedded systems
Embedded Systems
Compiler
ROM
Reusability
3 Citations (Scopus)

Module selection using manufacturing information

Tomiyama, H. & Yasuura, H., Jan 1 1998, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E81-A, 12, p. 2576-2584 9 p.

Research output: Contribution to journalArticle

Manufacturing
High-level Synthesis
Module
Chip
Unit
1 Citation (Scopus)

Module selection using manufacturing information

Tomiyama, H. & Yasuura, H., 1998, In : Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 275-281 7 p.

Research output: Contribution to journalArticle

Costs
High level synthesis
48 Citations (Scopus)

Novel test methodology for core-based system LSIs and a testing time minimization problem

Sugihara, M., Date, H. & Yasuura, H., Dec 1 1998, IEEE International Test Conference (TC). Anon (ed.). p. 465-472 8 p. (IEEE International Test Conference (TC)).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Built-in self test
Testing
Combinatorial optimization
5 Citations (Scopus)

Power-Pro: Programmable Power Management Architecture

Ishihara, T. & Yasuura, H., Dec 1 1998, p. 321-322. 2 p.

Research output: Contribution to conferencePaper

Application programs
Clocks
Electric potential
Power management
8 Citations (Scopus)

Programmable power management architecture for power reduction

Ishihara, T. & Yasuura, H., Jan 1 1998, In : IEICE Transactions on Electronics. E81-C, 9, p. 1473-1479 7 p.

Research output: Contribution to journalArticle

Clocks
Electric potential
Microprocessor chips
Electric power utilization
Power management
9 Citations (Scopus)

Program slicing on vhdl descriptions and its evaluation

Ichinoset, S., Iwaihara, M. & Yasuura, H., Jan 1 1998, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E81-A, 12, p. 2585-2594 10 p.

Research output: Contribution to journalArticle

Program Slicing
Computer hardware description languages
Evaluation
Slicing
Reuse
17 Citations (Scopus)

Soft-core processor architecture for embedded system design

Nurprasetyo, E. F., Inoue, A., Tomiyama, H. & Yasuura, H., Jan 1 1998, In : IEICE Transactions on Electronics. E81-C, 9, p. 1416-1422 7 p.

Research output: Contribution to journalArticle

Embedded systems
Systems analysis
Costs
Experiments
3 Citations (Scopus)

Statistical performance-driven module binding in high-level synthesis

Tomiyama, H., Inoue, A. & Yasuura, H., Dec 2 1998, Proceedings of the 11th International Symposium on System Synthesis, ISSS 1998. IEEE Computer Society, Vol. Part F129250. p. 66-71 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Networks (circuits)
Clocks
Fabrication
High level synthesis
Costs
142 Citations (Scopus)

Voltage scheduling problem for dynamically variable voltage processors

Ishihara, T. & Yasuura, H., 1998, Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers. Anon (ed.). IEEE

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Scheduling
Electric potential
Application programs
Linear programming
Energy utilization
1997
36 Citations (Scopus)

Code placement techniques for cache miss rate reduction

Tomiyama, H. & Yasuura, H., Jan 1 1997, In : ACM Transactions on Design Automation of Electronic Systems. 2, 4, p. 410-429 20 p.

Research output: Contribution to journalArticle

Cache memory
Embedded systems
Linear programming
Electric power utilization
Data storage equipment
6 Citations (Scopus)

Embedded system cost optimization via data path width adjustment

Shackleford, B., Yasuda, M., Okushi, E., Koizumi, H., Tomiyama, H., Inoue, A. & Yasuura, H., Jan 1 1997, In : IEICE Transactions on Information and Systems. E80-D, 10, p. 974-981 8 p.

Research output: Contribution to journalArticle

Computer peripheral equipment
Cost reduction
Application programs
Embedded systems
Computer hardware

HW/SW co-design environment for multi-media equipments development using inverse problem

Suzuki, F., Koizumi, H., Hiramine, M., Yamamoto, K., Yasuura, H. & Okino, K., 1997, Hardware/Software Codesign - Proceedings of the International Workshop. Anon (ed.). IEEE, p. 153-157 5 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Inverse problems
Semiconductor materials
Television receivers
Numerical models
Hardware
16 Citations (Scopus)

Memory-CPU size optimization for embedded system designs

Shackleford, B., Yasuda, M., Okushi, E., Koizumi, H., Tomiyama, H. & Yasuura, H., Jan 1 1997, In : Proceedings - Design Automation Conference. p. 246-251 6 p.

Research output: Contribution to journalConference article

Computer peripheral equipment
Cost reduction
Application programs
Embedded systems
Computer hardware
1 Citation (Scopus)

Method for reconfigurable multimedia equipment development using inverse problem

Suzuki, F., Koizumi, H., Nishino, K. & Yasuura, H., Dec 1 1997, p. 74-80. 7 p.

Research output: Contribution to conferencePaper

Inverse problems
Television receivers
Reconfigurable architectures
Human engineering
Networks (circuits)

Rapid prototyping method for top-down design of system-on-chip devices using LPGAs

Suzuki, F., Koizumi, H., Seo, K., Yasuura, H., Hiramine, M., Okino, K. & Or-Bach, Z., 1997, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. IEEE, p. 9-18 10 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Rapid prototyping
Lasers
Liquid crystal displays
Tuning
System-on-chip
1996
Plant layout
Digital circuits
Microprocessor chips
Logic Synthesis
1 Citation (Scopus)

Basic experimentation on accuracy of power estimation for CMOS VLSI circuits

Ishihara, T. & Yasuura, H., 1996, International Symposium on Low Power Electronics and Design, Digest of Technical Papers. IEEE, p. 117-120 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

VLSI circuits
Energy dissipation
Electric power utilization
Microprocessor chips
Clocks

Basic experimentation on accuracy of power estimation for CMOS VLSI circuits

Ishihara, T. & Yasuura, H., Dec 1 1996, p. 117-120. 4 p.

Research output: Contribution to conferencePaper

VLSI circuits
Energy dissipation
Electric power utilization
Microprocessor chips
Clocks
11 Citations (Scopus)

Comparison of parallel multipliers with neuron MOS and CMOS technologies

Hirose, K. & Yasuura, H., 1996, IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings. IEEE, p. 488-491 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

MOSFET devices
Neurons
Logic circuits
Adders
Networks (circuits)
1 Citation (Scopus)

On the computational power of binary decision diagram with redundant variables

Yamada, T. & Yasuura, H., Jan 1 1996, In : Formal Methods in System Design. 8, 1, p. 65-89 25 p.

Research output: Contribution to journalArticle

Binary decision diagrams
Decision Diagrams
Logarithmic
Polynomials
Binary

Optimal code placement of embedded software for instruction caches

Tomiyama, H. & Yasuura, H., Mar 11 1996, Proceedings of the 1996 European Conference on Design and Test, EDTC 1996. Association for Computing Machinery, Inc, p. 96-101 6 p. 494132. (Proceedings of the 1996 European Conference on Design and Test, EDTC 1996).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Embedded software
Linear programming
23 Citations (Scopus)

Optimal code placement of embedded software for instruction caches

Tomiyama, H. & Yasuura, H., Jan 1 1996, In : Proceedings of European Design and Test Conference. p. 96-101 6 p.

Research output: Contribution to journalConference article

Embedded software
Linear programming
11 Citations (Scopus)

Satsuki: An integrated processor synthesis and compiler generation system

Shackleford, B., Yasuda, M., Okushi, E., Koizumi, H., Tomiyama, H. & Yasuura, H., 1996, In : IEICE Transactions on Information and Systems. E79-D, 10, p. 1373-1381 9 p.

Research output: Contribution to journalArticle

Computer peripheral equipment
Application programs
Computer hardware
Costs
Computer systems
7 Citations (Scopus)

Size-constrained code placement for cache miss rate reduction

Tomiyama, H. & Yasuura, H., Dec 1 1996, In : Proceedings of the International Symposium on System Synthesis. p. 96-101 6 p.

Research output: Contribution to journalConference article

Embedded systems
Electric power utilization
1995
7 Citations (Scopus)

Proposal for a co-design method in control systems using combination of models

Koizumi, H., Seo, K., Suzuki, F., Ohtsuru, Y. & Yasuura, H., Mar 1995, In : IEICE Transactions on Information and Systems. E78-D, 3, p. 237-247 11 p.

Research output: Contribution to journalArticle

Control systems
Systems analysis
1994

Behavioral verification of cpus using functional information extraction

Ohmura, M., Tamaru, K. & Yasuura, H., Jan 1 1994, In : Electronics and Communications in Japan (Part III: Fundamental Electronic Science). 77, 3, p. 52-61 10 p.

Research output: Contribution to journalArticle

Program processors
Networks (circuits)
Logic circuits
Microprocessor chips
Computer aided design
1993
1 Citation (Scopus)

A micro-vectorprocessor Architecture - Performance Modeling and Benchmarking -

Hashimoto, T., Hironaka, T., Murakami, K. & Yasuura, H., Aug 1 1993, Proceedings of the 7th International Conference on Supercomputing, ICS 1993. Association for Computing Machinery, p. 308-317 10 p. (Proceedings of the International Conference on Supercomputing; vol. Part F129670).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Benchmarking
Bandwidth
Data storage equipment
4 Citations (Scopus)

Bit-parallel block-parallel functional memory type parallel processor architecture

Kobayashi, K., Tamaru, K., Yasuura, H. & Onodera, H., Jul 1 1993, In : IEICE Transactions on Electronics. E76-C, 7, p. 1151-1158 8 p.

Research output: Contribution to journalArticle

Data storage equipment
Parallel architectures
Associative storage
18 Citations (Scopus)

COACH: a computer aided design tool for computer architects

Akaboshi, H. & Yasuura, H., Oct 1 1993, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E76-A, 10, p. 1760-1769 10 p.

Research output: Contribution to journalArticle

Computer-aided Design
Computer aided design
Compiler
Hardware
Layout
1992

A new VLSI algorithm for high throughput image filtering

Islam, F. F., Yasuura, H. & Tamaru, K., Jan 1 1992, 1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992. Institute of Electrical and Electronics Engineers Inc., p. 2441-2444 4 p. 230523. (Proceedings - IEEE International Symposium on Circuits and Systems; vol. 5).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Throughput
Masks
Pixels
Logic gates
1991

Functional information extraction from combinational circuits

Ohmura, M., Yasuura, H. & Tamaru, K., Jan 1 1991, In : Electronics and Communications in Japan (Part III: Fundamental Electronic Science). 74, 11, p. 28-38 11 p.

Research output: Contribution to journalArticle

Combinatorial circuits
Networks (circuits)
Binary decision diagrams
Logic design
Logic circuits

Locally computable coding for unary operations

Yasuura, H., Jan 1 1991, Concurrency: Theory, Language, and Architecture - UK/Japan Workshop, Proceedings. Ito, T. & Yonezawa, A. (eds.). Springer Verlag, p. 312-323 12 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 491 LNCS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Unary
State assignment
Redundancy
Coding
Parallel algorithms