• 1877 Citations
  • 19 h-Index
1978 …2017
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Research Output 1978 2017

1990
2 Citations (Scopus)

NES: The behavioral model for the formal semantics of a hardware design language UDL/I

Ishiura, N., Yasuura, H. & Yajima, S., 1990, 27th ACM/IEEE Design Automation Conference. Proceedings 1990. Publ by IEEE, p. 8-13 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Semantics
Hardware
Computer hardware description languages
1989
2 Citations (Scopus)

Semantics of a hardware design language for Japanese standardization

Yasuura, H. & Ishiura, N., 1989, In : Proceedings - Design Automation Conference. p. 836-839 4 p.

Research output: Contribution to journalArticle

Standardization
Semantics
Hardware
Linguistics
Simulators
1988
3 Citations (Scopus)

Parallel exhaustive search for several np-complete problems using content addressable memories

Yasuura, H., Tsujimoto, T. & Tamaru, K., Dec 1 1988, Proceedings - IEEE International Symposium on Circuits and Systems. Publ by IEEE, p. 333-336 4 p. (Proceedings - IEEE International Symposium on Circuits and Systems; vol. 1).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Associative storage
Parallel algorithms
Computational complexity
1987
13 Citations (Scopus)

High-Speed Logic Simulation on Vector Processors

Ishiura, N., Yasuura, H. & Yajima, S., Jan 1 1987, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 6, 3, p. 305-321 17 p.

Research output: Contribution to journalArticle

Sequential circuits
Circuit simulation
Combinatorial circuits
Supercomputers
Processing

On high‐speed parallel algorithms using redundant coding

Yasuura, H., Takagi, N. & Yajima, S., Jan 1 1987, In : Systems and Computers in Japan. 18, 12, p. 72-80 9 p.

Research output: Contribution to journalArticle

Parallel algorithms
Parallel Algorithms
High Speed
Coding
Computability
1985
3 Citations (Scopus)

HIGH-SPEED LOGIC SIMULATION ON A VECTOR PROCESSOR.

Ishiura, N., Yasuura, H., Kawata, T. & Yajima, S., 1985, Unknown Host Publication Title. IEEE, p. 119-121 3 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Logic design
Computer aided design
Pipelines
Simulators
Engines
233 Citations (Scopus)

High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree

Takagi, N., Yasuura, H. & Yajima, S., 1985, In : IEEE Transactions on Computers. C-34, 9, p. 789-796 8 p.

Research output: Contribution to journalArticle

Trees (mathematics)
Multiplier
Multiplication
High Speed
Binary
9 Citations (Scopus)

On the area-time optimal design of l-selectors

Thompson, C. D. & Yasuura, H., Jan 1 1985, Conference Record - 19th Asilomar Conference on Circuits, Systems and Computers, ACSSC 1985. Kirk, D. E. (ed.). IEEE Computer Society, p. 365-368 4 p. 671482. (Conference Record - Asilomar Conference on Signals, Systems and Computers).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Networks (circuits)
Optimal design
1984
1 Citation (Scopus)

HARDWARE ALGORITHMS FOR VLSI SYSTEMS.

Yasuura, H. & Yajima, S., 1984, Lecture Notes in Computer Science. Springer-Verlag, p. 105-129 25 p.

Research output: Chapter in Book/Report/Conference proceedingChapter

Hardware
Computer hardware description languages
Networks (circuits)
Logic circuits
18 Citations (Scopus)

ON PARALLEL COMPUTATIONAL COMPLEXITY OF UNIFICATION.

Yasuura, H., 1984, Unknown Host Publication Title. Ohmsha Ltd, p. 235-243 9 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Parallel algorithms
Computational complexity
Combinatorial circuits
Logic circuits
Polynomials
8 Citations (Scopus)

TIME FIRST EVALUATION ALGORITHM FOR HIGH-SPEED LOGIC SIMULATION.

Ishiura, N., Yasuura, H. & Yajima, S., 1984, Unknown Host Publication Title. IEEE, p. 197-199 3 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Networks (circuits)
1983

Hardware algorithms and logic design automation: An overview and progress report

Yajima, S. & Yasuura, H., Jan 1 1983, RIMS Symposia on Software Science and Engineering - Proceedings. Nakajima, R., Nakata, I., Goto, E., Furukawa, K. & Yonezawa, A. (eds.). Springer Verlag, p. 147-164 18 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 147 LNCS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Logic Design
Design Automation
Logic design
Hardware Design
Algorithm Design
2 Citations (Scopus)

VLSI-ORIENTED HIGH-SPEED MULTIPLIER USING A REDUNDANT BINARY ADDITION TREE.

Takagi, N., Yasuura, H. & Yajima, S., Jan 1 1983, In : Systems, computers, controls. 14, 4, p. 19-28 10 p.

Research output: Contribution to journalArticle

Binary trees
Adders
1982
2 Citations (Scopus)

An interactive simulation system for structured logic design - ISS

Sakai, T., Tsuchida, Y., Yasuura, H., Ooi, Y., Ono, Y., Kano, H., Kimura, S. & Yajima, S., Jan 1 1982, In : Proceedings - Design Automation Conference. p. 747-754 8 p.

Research output: Contribution to journalConference article

Logic Design
Interactive Simulation
Logic design
Interactive Systems
Simulation System

ON THE AREA OF LOGIC CIRCUITS IN VLSI.

Yasuura, H. & Yajima, S., Jul 1982, In : Systems, computers, controls. 13, 4, p. 101-110 10 p.

Research output: Contribution to journalArticle

Logic circuits
Networks (circuits)
Logic design
Combinatorial circuits
VLSI circuits
30 Citations (Scopus)

The Parallel Enumeration Sorting Scheme for VLSI

Yasuura, H., Takagi, N. & Yajima, S., Jan 1 1982, In : IEEE Transactions on Computers. C-31, 12, p. 1192-1201 10 p.

Research output: Contribution to journalArticle

Sorting
Enumeration
Networks (circuits)
Cellular arrays
Data storage equipment
1981
24 Citations (Scopus)

SCHEDULING OF PAGE-FETCHES IN JOIN OPERATIONS.

Merrett, T. H., Kambayashi, Y. & Yasuura, H., 1981, Very Large Data Bases, International Conference on Very Large Data Bases. IEEE Comput Soc Press (n 371), p. 488-498 11 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Scheduling
1 Citation (Scopus)

Width and depth of combinational logic circuits

Yasuura, H., Jan 1 1981, In : Information Processing Letters. 13, 4-5, p. 191-194 4 p.

Research output: Contribution to journalArticle

Circuit Complexity
Combinatorial circuits
Logic circuits
Parallel Computation
Logic
1979

ON THE DEPTH OF COMBINATIONAL CIRCUITS REQUIRED TO COMPUTE SWITCHING FUNCTIONS.

Yasuura, H. & Yajima, S., Sep 1979, In : Systems, computers, controls. 10, 5, p. 1-10 10 p.

Research output: Contribution to journalArticle

Switching functions
Combinatorial circuits
Formal languages
Polynomials
1978

DESIGN OF ASYNCHRONOUS ARBITERS FROM THE STANDPOINT OF ASYNCHRONOUS SEQUENTIAL CIRCUIT THEORY.

Yasuura, H. & Yajima, S., Jan 1 1978, In : Systems, computers, controls. 9, 6, p. 71-78 8 p.

Research output: Contribution to journalArticle

Sequential circuits
Circuit theory