• 1891 Citations
  • 19 h-Index
1978 …2017
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Research Output 1978 2017

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Article
Article
6 Citations (Scopus)
Crosstalk
Wire
Telecommunication repeaters
SPICE
Switches
1 Citation (Scopus)
Embedded systems
Embedded Systems
Optimization Techniques
Data storage equipment
ROM
2 Citations (Scopus)

A module generator of 2-level neuron MOS circuits

Ike, K., Hirose, K. & Yasuura, H., Jan 1 1998, In : Computers and Electrical Engineering. 24, 1-2, p. 33-41 9 p.

Research output: Contribution to journalArticle

Neurons
Networks (circuits)
MOSFET devices
Transistors
1 Citation (Scopus)
Smart cards
Smart Card
One-way Hash Function
Function generators
Pseudorandom number Generator
1 Citation (Scopus)

An optimization technique for low-energy embedded memory systems

Matsumura, T., Ishihara, T. & Yasuura, H., Dec 1 2009, In : IPSJ Transactions on System LSI Design Methodology. 2, p. 239-249 11 p.

Research output: Contribution to journalArticle

Computer systems
Data storage equipment
Energy utilization
Memory architecture
Static random access storage
2 Citations (Scopus)

A power reduction scheme for data buses by dynamic detection of active bits

Muroyama, M., Hyodo, A., Okuma, T. & Yasuura, H., Apr 2004, In : IEICE Transactions on Electronics. E87-C, 4, p. 598-605 8 p.

Research output: Contribution to journalArticle

Electric power utilization

A proposal of secure information infrastructure based on PID

Hamasaki, Y. & Yasuura, H., Sep 1 2002, In : Research Reports on Information Science and Electrical Engineering of Kyushu University. 7, 2, p. 139-148 10 p.

Research output: Contribution to journalArticle

A selective replacement method for timing-error-predicting flip-flops

Kunitake, Y., Sato, T., Yasuura, H. & Hayashida, T., Oct 1 2012, In : Journal of Circuits, Systems and Computers. 21, 6, 1240013.

Research output: Contribution to journalArticle

Flip flop circuits
Redundancy
Electric power utilization
Electric potential
Transistors
1 Citation (Scopus)

A software technique to improve lifetime of caches containing ultra-leaky SRAM cells caused by within-die Vth variation

Goudarzi, M., Ishihara, T. & Yasuura, H., Dec 1 2008, In : Microelectronics Journal. 39, 12, p. 1797-1808 12 p.

Research output: Contribution to journalArticle

Static random access storage
Transistors
transistors
computer programs
life (durability)
7 Citations (Scopus)

A test methodology for core-based system lsis

Sugihara, M., Date, H. & Yasuura, H., Jan 1 1998, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E81-A, 12, p. 2640-2645 6 p.

Research output: Contribution to journalArticle

Built-in self test
Methodology
Testing
Built-in Self-test
Combinatorial optimization
Plant layout
Digital circuits
Microprocessor chips
Logic Synthesis

Behavioral verification of cpus using functional information extraction

Ohmura, M., Tamaru, K. & Yasuura, H., Jan 1 1994, In : Electronics and Communications in Japan (Part III: Fundamental Electronic Science). 77, 3, p. 52-61 10 p.

Research output: Contribution to journalArticle

Program processors
Networks (circuits)
Logic circuits
Microprocessor chips
Computer aided design
4 Citations (Scopus)

Bit-parallel block-parallel functional memory type parallel processor architecture

Kobayashi, K., Tamaru, K., Yasuura, H. & Onodera, H., Jul 1 1993, In : IEICE Transactions on Electronics. E76-C, 7, p. 1151-1158 8 p.

Research output: Contribution to journalArticle

Data storage equipment
Parallel architectures
Associative storage

Bitwidth optimization for low power digital FIR filter design

Tarumi, K., Hyodo, A., Muroyama, M. & Yasuura, H., Jan 1 2005, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E88-A, 4, p. 869-875 7 p.

Research output: Contribution to journalArticle

FIR Filter
Digital Filter
Filter Design
FIR filters
Digital filters
18 Citations (Scopus)

COACH: a computer aided design tool for computer architects

Akaboshi, H. & Yasuura, H., Oct 1 1993, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E76-A, 10, p. 1760-1769 10 p.

Research output: Contribution to journalArticle

Computer-aided Design
Computer aided design
Compiler
Hardware
Layout
9 Citations (Scopus)

Code and data placement for embedded processors with scratchpad and cache memories

Ishitobi, Y., Ishihara, T. & Yasuura, H., Aug 1 2010, In : Journal of Signal Processing Systems. 60, 2, p. 211-224 14 p.

Research output: Contribution to journalArticle

Data Placement
Cache memory
Embedded Processor
Energy utilization
Energy Consumption
36 Citations (Scopus)

Code placement techniques for cache miss rate reduction

Tomiyama, H. & Yasuura, H., Jan 1 1997, In : ACM Transactions on Design Automation of Electronic Systems. 2, 4, p. 410-429 20 p.

Research output: Contribution to journalArticle

Cache memory
Embedded systems
Linear programming
Electric power utilization
Data storage equipment

DESIGN OF ASYNCHRONOUS ARBITERS FROM THE STANDPOINT OF ASYNCHRONOUS SEQUENTIAL CIRCUIT THEORY.

Yasuura, H. & Yajima, S., Jan 1 1978, In : Systems, computers, controls. 9, 6, p. 71-78 8 p.

Research output: Contribution to journalArticle

Sequential circuits
Circuit theory

Educational results of hardware course with FPGAs

Sawada, S., Tomiyasu, H. & Yasuura, H., Mar 1 1999, In : Research Reports on Information Science and Electrical Engineering of Kyushu University. 4, 1, p. 87-92 6 p.

Research output: Contribution to journalArticle

Field programmable gate arrays (FPGA)
Students
Hardware
Microprocessor chips
Control facilities
6 Citations (Scopus)

Embedded system cost optimization via data path width adjustment

Shackleford, B., Yasuda, M., Okushi, E., Koizumi, H., Tomiyama, H., Inoue, A. & Yasuura, H., Jan 1 1997, In : IEICE Transactions on Information and Systems. E80-D, 10, p. 974-981 8 p.

Research output: Contribution to journalArticle

Computer peripheral equipment
Cost reduction
Application programs
Embedded systems
Computer hardware
14 Citations (Scopus)

Embedded system design using soft-core processor and Valen-C

Yasuura, H., Tomiyama, H., Inoue, A. & Eko Fajar, N., Sep 1 1998, In : Journal of Information Science and Engineering. 14, 3, p. 587-603 17 p.

Research output: Contribution to journalArticle

Embedded systems
Systems analysis
ROM
Random access storage
programming language
1 Citation (Scopus)

Enhancements of a circuit-level timing speculation technique and their evaluations using a co-simulation environment

Kunitake, Y., Mima, K., Sato, T. & Yasuura, H., 2009, In : IEICE Transactions on Electronics. E92-C, 4, p. 483-491 9 p.

Research output: Contribution to journalArticle

Networks (circuits)
Delay circuits
Semiconductor materials
2 Citations (Scopus)

Flexible system LSI for embedded systems and its optimization techniques

Inoue, A., Ishihara, T. & Yasuura, H., Jun 1 2000, In : Design Automation for Embedded Systems. 5, 2, p. 179-205 27 p.

Research output: Contribution to journalArticle

Embedded systems
Costs
Masks
Fabrication
Electric power utilization

Functional information extraction from combinational circuits

Ohmura, M., Yasuura, H. & Tamaru, K., Jan 1 1991, In : Electronics and Communications in Japan (Part III: Fundamental Electronic Science). 74, 11, p. 28-38 11 p.

Research output: Contribution to journalArticle

Combinatorial circuits
Networks (circuits)
Binary decision diagrams
Logic design
Logic circuits
Random access storage
Data storage equipment
Parallel algorithms
Transistors
Computer systems
13 Citations (Scopus)

High-Speed Logic Simulation on Vector Processors

Ishiura, N., Yasuura, H. & Yajima, S., May 1987, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 6, 3, p. 305-321 17 p.

Research output: Contribution to journalArticle

Sequential circuits
Circuit simulation
Combinatorial circuits
Supercomputers
Processing
238 Citations (Scopus)

High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree

Takagi, N., Yasuura, H. & Yajima, S., 1985, In : IEEE Transactions on Computers. C-34, 9, p. 789-796 8 p.

Research output: Contribution to journalArticle

Trees (mathematics)
Multiplier
Multiplication
High Speed
Binary
5 Citations (Scopus)

Instruction scheduling to reduce switching activity of off-chip buses for low-power systems with caches

Tomiyama, H., Ishihara, T., Inoue, A. & Yasuura, H., Jan 1 1998, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E81-A, 12, p. 2621-2629 9 p.

Research output: Contribution to journalArticle

Instruction Scheduling
Power System
Cache
Chip
Capacitance
23 Citations (Scopus)

Language and compiler for optimizing datapath widths of embedded systems

Inoue, A., Tomiyama, H., Okuma, T., Kanbara, H. & Yasuura, H., Jan 1 1998, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E81-A, 12, p. 2595-2604 10 p.

Research output: Contribution to journalArticle

Embedded systems
Embedded Systems
Compiler
ROM
Reusability

Leakage Power Reduction for Battery-Operated Portable Systems

Cao, Y. & Yasuura, H., Dec 2003, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E86-A, 12, p. 3200-3203 4 p.

Research output: Contribution to journalArticle

Leakage
Battery
Low-power Design
Parameter Design
Penalty

Memory organization for low-energy processor-based application-specific systems

Cao, Y. & Yasuura, H., Aug 2002, In : IEICE Transactions on Electronics. E85-C, 8, p. 1616-1624 9 p.

Research output: Contribution to journalArticle

Data storage equipment
Random access storage
Data transfer
3 Citations (Scopus)

Module selection using manufacturing information

Tomiyama, H. & Yasuura, H., Jan 1 1998, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E81-A, 12, p. 2576-2584 9 p.

Research output: Contribution to journalArticle

Manufacturing
High-level Synthesis
Module
Chip
Unit

On high‐speed parallel algorithms using redundant coding

Yasuura, H., Takagi, N. & Yajima, S., 1987, In : Systems and Computers in Japan. 18, 12, p. 72-80 9 p.

Research output: Contribution to journalArticle

Parallel algorithms
Parallel Algorithms
High Speed
Coding
Computability

ON THE AREA OF LOGIC CIRCUITS IN VLSI.

Yasuura, H. & Yajima, S., Jan 1 1982, In : Systems, computers, controls. 13, 4, p. 101-110 10 p.

Research output: Contribution to journalArticle

Logic circuits
Networks (circuits)
Logic design
Combinatorial circuits
VLSI circuits
1 Citation (Scopus)

On the computational power of binary decision diagram with redundant variables

Yamada, T. & Yasuura, H., Jan 1 1996, In : Formal Methods in System Design. 8, 1, p. 65-89 25 p.

Research output: Contribution to journalArticle

Binary decision diagrams
Decision Diagrams
Logarithmic
Polynomials
Binary

ON THE DEPTH OF COMBINATIONAL CIRCUITS REQUIRED TO COMPUTE SWITCHING FUNCTIONS.

Yasuura, H. & Yajima, S., Sep 1979, In : Systems, computers, controls. 10, 5, p. 1-10 10 p.

Research output: Contribution to journalArticle

Switching functions
Combinatorial circuits
Formal languages
Polynomials
Built-in self test
Optimization
Bandwidth
Scheduling
Hardware

Password based anonymous authentication with private information retrieval

Nakamura, T., Inenaga, S., Ikeda, D., Baba, K. & Yasuura, H., Apr 1 2011, In : Journal of Digital Information Management. 9, 2, p. 72-78 7 p.

Research output: Contribution to journalArticle

Information retrieval
information retrieval
Authentication
service provider
Private information
1 Citation (Scopus)

Pre-route power analysis techniques for SoC

Yamada, T., Sakamoto, T., Furuichi, S., Mukuno, M., Matsushita, Y. & Yasuura, H., Jan 1 2003, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E86-A, 3, p. 686-692 7 p.

Research output: Contribution to journalArticle

Power Analysis
Transistors
Chip
Clocks
Capacitance
8 Citations (Scopus)

Programmable power management architecture for power reduction

Ishihara, T. & Yasuura, H., Jan 1 1998, In : IEICE Transactions on Electronics. E81-C, 9, p. 1473-1479 7 p.

Research output: Contribution to journalArticle

Clocks
Electric potential
Microprocessor chips
Electric power utilization
Power management
9 Citations (Scopus)

Program slicing on vhdl descriptions and its evaluation

Ichinoset, S., Iwaihara, M. & Yasuura, H., Jan 1 1998, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E81-A, 12, p. 2585-2594 10 p.

Research output: Contribution to journalArticle

Program Slicing
Computer hardware description languages
Evaluation
Slicing
Reuse
7 Citations (Scopus)

Proposal for a co-design method in control systems using combination of models

Koizumi, H., Seo, K., Suzuki, F., Ohtsuru, Y. & Yasuura, H., Mar 1 1995, In : IEICE Transactions on Information and Systems. E78-D, 3, p. 237-247 11 p.

Research output: Contribution to journalArticle

Control systems
Systems analysis

Quality-driven design for video applications

Cao, Y. & Yasuura, H., Jan 1 2002, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E85-A, 12, p. 2568-2576 9 p.

Research output: Contribution to journalArticle

MPEG-2
Optimization
Methodology
Design Methodology
Reuse
6 Citations (Scopus)

Reduction of Coupling Effects by Optimizing the 3-D Configuration of the Routing Grid

Sakai, A., Yamada, T., Matsushita, Y. & Yasuura, H., Oct 1 2003, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 11, 5, p. 951-954 4 p.

Research output: Contribution to journalArticle

Crosstalk
Electric power utilization
Multilayers
Image processing
Networks (circuits)
1 Citation (Scopus)

Routing Methodology for Minimizing Crosstalk in SoC

Yamada, T., Sakai, A., Matsushita, Y. & Yasuura, H., Sep 2003, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E86-A, 9, p. 2347-2356 10 p.

Research output: Contribution to journalArticle

Crosstalk
Routing
Chip
Methodology
Optimization Techniques
11 Citations (Scopus)

Satsuki: An integrated processor synthesis and compiler generation system

Shackleford, B., Yasuda, M., Okushi, E., Koizumi, H., Tomiyama, H. & Yasuura, H., Jan 1 1996, In : IEICE Transactions on Information and Systems. E79-D, 10, p. 1373-1381 9 p.

Research output: Contribution to journalArticle

Computer peripheral equipment
Application programs
Computer hardware
Costs
Computer systems
2 Citations (Scopus)

Semantics of a hardware design language for Japanese standardization

Yasuura, H. & Ishiura, N., 1989, In : Proceedings - Design Automation Conference. p. 836-839 4 p.

Research output: Contribution to journalArticle

Standardization
Semantics
Hardware
Linguistics
Simulators
1 Citation (Scopus)

Short term cell-flipping technique for mitigating SNM degradation due to NBTI

Kunitake, Y., Sato, T. & Yasuura, H., Jan 1 2011, In : IEICE Transactions on Electronics. E94-C, 4, p. 520-529 10 p.

Research output: Contribution to journalArticle

Static random access storage
Transistors
Threshold voltage
Degradation
Recovery

Single-cycle-accessible two-level caches and compilation technique for energy reducion

Yamaguchi, S., Ishitobi, Y., Ishihara, T. & Yasuura, H., Dec 1 2009, In : IPSJ Transactions on System LSI Design Methodology. 2, p. 189-199 11 p.

Research output: Contribution to journalArticle

Energy utilization
Data storage equipment
Degradation
Experiments
17 Citations (Scopus)

Soft-core processor architecture for embedded system design

Nurprasetyo, E. F., Inoue, A., Tomiyama, H. & Yasuura, H., Jan 1 1998, In : IEICE Transactions on Electronics. E81-C, 9, p. 1416-1422 7 p.

Research output: Contribution to journalArticle

Embedded systems
Systems analysis
Costs
Experiments