• 1891 Citations
  • 19 h-Index
1978 …2017
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Research Output 1978 2017

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Article
1989
2 Citations (Scopus)

Semantics of a hardware design language for Japanese standardization

Yasuura, H. & Ishiura, N., 1989, In : Proceedings - Design Automation Conference. p. 836-839 4 p.

Research output: Contribution to journalArticle

Standardization
Semantics
Hardware
Linguistics
Simulators
1987
13 Citations (Scopus)

High-Speed Logic Simulation on Vector Processors

Ishiura, N., Yasuura, H. & Yajima, S., May 1987, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 6, 3, p. 305-321 17 p.

Research output: Contribution to journalArticle

Sequential circuits
Circuit simulation
Combinatorial circuits
Supercomputers
Processing

On high‐speed parallel algorithms using redundant coding

Yasuura, H., Takagi, N. & Yajima, S., 1987, In : Systems and Computers in Japan. 18, 12, p. 72-80 9 p.

Research output: Contribution to journalArticle

Parallel algorithms
Parallel Algorithms
High Speed
Coding
Computability
1985
238 Citations (Scopus)

High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree

Takagi, N., Yasuura, H. & Yajima, S., 1985, In : IEEE Transactions on Computers. C-34, 9, p. 789-796 8 p.

Research output: Contribution to journalArticle

Trees (mathematics)
Multiplier
Multiplication
High Speed
Binary
1983
2 Citations (Scopus)

VLSI-ORIENTED HIGH-SPEED MULTIPLIER USING A REDUNDANT BINARY ADDITION TREE.

Takagi, N., Yasuura, H. & Yajima, S., Jan 1 1983, In : Systems, computers, controls. 14, 4, p. 19-28 10 p.

Research output: Contribution to journalArticle

Binary trees
Adders
1982

ON THE AREA OF LOGIC CIRCUITS IN VLSI.

Yasuura, H. & Yajima, S., Jan 1 1982, In : Systems, computers, controls. 13, 4, p. 101-110 10 p.

Research output: Contribution to journalArticle

Logic circuits
Networks (circuits)
Logic design
Combinatorial circuits
VLSI circuits
30 Citations (Scopus)

The Parallel Enumeration Sorting Scheme for VLSI

Yasuura, H., Takagi, N. & Yajima, S., Jan 1 1982, In : IEEE Transactions on Computers. C-31, 12, p. 1192-1201 10 p.

Research output: Contribution to journalArticle

Sorting
Enumeration
Networks (circuits)
Cellular arrays
Data storage equipment
1981
1 Citation (Scopus)

Width and depth of combinational logic circuits

Yasuura, H., 1981, In : Information Processing Letters. 13, 4-5, p. 191-194 4 p.

Research output: Contribution to journalArticle

Circuit Complexity
Combinatorial circuits
Logic circuits
Parallel Computation
Logic
1979

ON THE DEPTH OF COMBINATIONAL CIRCUITS REQUIRED TO COMPUTE SWITCHING FUNCTIONS.

Yasuura, H. & Yajima, S., Sep 1979, In : Systems, computers, controls. 10, 5, p. 1-10 10 p.

Research output: Contribution to journalArticle

Switching functions
Combinatorial circuits
Formal languages
Polynomials
1978

DESIGN OF ASYNCHRONOUS ARBITERS FROM THE STANDPOINT OF ASYNCHRONOUS SEQUENTIAL CIRCUIT THEORY.

Yasuura, H. & Yajima, S., Jan 1 1978, In : Systems, computers, controls. 9, 6, p. 71-78 8 p.

Research output: Contribution to journalArticle

Sequential circuits
Circuit theory