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Research Output 1986 2019

2019

An Efficient SAT-Attack Algorithm Against Logic Encryption

Matsunaga, Y. & Yoshimura, M., Jul 2019, 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design, IOLTS 2019. Gizopoulos, D., Alexandrescu, D., Papavramidou, P. & Maniatakos, M. (eds.). Institute of Electrical and Electronics Engineers Inc., p. 44-47 4 p. 8854466. (2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design, IOLTS 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Cryptography
Program processors
Networks (circuits)
Experiments
2017

An accelerating technique for SAT-based ATPG

Matsunaga, Y., Feb 1 2017, In : IPSJ Transactions on System LSI Design Methodology. 10, p. 39-44 6 p.

Research output: Contribution to journalArticle

Automatic test pattern generation
2016
Program processors
Counterexample
Encoding
Refinement
Networks (circuits)
Compaction
Grouping
Fault
Compatibility
Efficient Algorithms
2015
6 Citations (Scopus)

Accelerating SAT-based Boolean matching for heterogeneous FPGAs using one-hot encoding and CEGAR technique

Matsunaga, Y., Mar 11 2015, 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015. Institute of Electrical and Electronics Engineers Inc., p. 255-260 6 p. 7059014. (20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Field Programmable Gate Array
Program processors
Counterexample
Field programmable gate arrays (FPGA)
Encoding
2014
4 Citations (Scopus)
Generator
Synthesis
Multi-valued Logic
Hardware
Latency
3 Citations (Scopus)

Synthesis algorithm of parallel index generation units

Matsunaga, Y., 2014, Proceedings - Design, Automation and Test in Europe, DATE 2014. Institute of Electrical and Electronics Engineers Inc., 6800511

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hardware
2013
10 Citations (Scopus)

An exact approach for gpc-based compressor tree synthesis

Matsunaga, T., Kimura, S. & Matsunaga, Y., Jan 1 2013, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E96-A, 12, p. 2553-2560 8 p.

Research output: Contribution to journalArticle

Compressor
Adders
Compressors
Synthesis
Inductive logic programming (ILP)
2012

An exact estimation algorithm of error propagation probability for sequential circuits

Yoshimura, M., Akamine, Y. & Matsunaga, Y., Aug 17 2012, In : IPSJ Transactions on System LSI Design Methodology. 5, p. 63-70 8 p.

Research output: Contribution to journalArticle

Sequential circuits
Flip flop circuits
Linear equations
Networks (circuits)
Integrated circuits
Combinatorial circuits
Networks (circuits)
Observability
Redundancy
6 Citations (Scopus)

Neutron-induced soft error rate estimation for SRAM using PHITS

Yoshimoto, S., Amashita, T., Yoshimura, M., Matsunaga, Y., Yasuura, H., Izumi, S., Kawaguchi, H. & Yoshimoto, M., Nov 22 2012, Proceedings of the 2012 IEEE 18th International On-Line Testing Symposium, IOLTS 2012. p. 138-141 4 p. 6313859. (Proceedings of the 2012 IEEE 18th International On-Line Testing Symposium, IOLTS 2012).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Static random access storage
Neutrons
Data storage equipment
2011
3 Citations (Scopus)

A robust algorithm for pessimistic analysis of logic masking effects in combinational circuits

Takata, T. & Matsunaga, Y., Sep 19 2011, Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011. p. 246-251 6 p. 5994537

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Combinatorial circuits
Networks (circuits)
Redundancy
Heuristic algorithms

A soft error tolerance estimation method for sequential circuits

Yoshimura, M., Akamine, Y. & Matsunaga, Y., Dec 1 2011, Proceedings - 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011. p. 268-276 9 p. 6104452. (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Sequential circuits
Networks (circuits)
Linear equations
9 Citations (Scopus)

Multi-operand adder synthesis targeting FPGAs

Matsunaga, T., Kimura, S. & Matsunaga, Y., Jan 1 2011, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E94-A, 12, p. 2579-2586 8 p.

Research output: Contribution to journalArticle

Adders
Field Programmable Gate Array
Field programmable gate arrays (FPGA)
Synthesis
Application specific integrated circuits
10 Citations (Scopus)

Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure

Yoshimoto, S., Amashita, T., Kozuwa, D., Takata, T., Yoshimura, M., Matsunaga, Y., Yasuura, H., Kawaguchi, H. & Yoshimoto, M., Sep 19 2011, Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011. p. 151-156 6 p. 5993829. (Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Static random access storage
Transistors
Error correction
Neutrons
Simulators
11 Citations (Scopus)

Power and delay aware synthesis of multi-operand adders targeting LUT-based FPGAs

Matsunaga, T., Kimura, S. & Matsunaga, Y., Sep 19 2011, IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011. p. 217-222 6 p. 5993639. (Proceedings of the International Symposium on Low Power Electronics and Design).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Adders
Compressors
Field programmable gate arrays (FPGA)
Inductive logic programming (ILP)
Application specific integrated circuits
2010
8 Citations (Scopus)

Multi-operand adder synthesis on FPGAs using generalized parallel counters

Matsunaga, T., Kimura, S. & Matsunaga, Y., Apr 28 2010, 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010. p. 337-342 6 p. 5419871. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Adders
Field programmable gate arrays (FPGA)
Application specific integrated circuits
Hardware
2009
1 Citation (Scopus)

An efficient cut enumeration for depth-optimum technology mapping for LUT-based FPGAs

Takata, T. & Matsunaga, Y., 2009, GLSVLSI 2009 - Proceedings of the 2009 Great Lakes Symposium on VLSI. p. 351-356 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Field programmable gate arrays (FPGA)
Merging
1 Citation (Scopus)

Area recovery under depth constraint for technology mapping for LUT-based FPGAs

Takata, T. & Matsunaga, Y., Dec 1 2009, In : IPSJ Transactions on System LSI Design Methodology. 2, p. 200-211 12 p.

Research output: Contribution to journalArticle

Heuristic algorithms
Field programmable gate arrays (FPGA)
Recovery

Binding refinement for multiplexer reduction

Kodama, S. & Matsunaga, Y., Dec 1 2009, In : IPSJ Transactions on System LSI Design Methodology. 2, p. 43-52 10 p.

Research output: Contribution to journalArticle

Tabu search
Networks (circuits)
Enumeration
Field Programmable Gate Array
Field programmable gate arrays (FPGA)
Heuristics
Merging

Framework for parallel prefix adder synthesis considering switching activities

Matsunaga, T., Kimura, S. & Matsunaga, Y., Dec 1 2009, In : IPSJ Transactions on System LSI Design Methodology. 2, p. 212-221 10 p.

Research output: Contribution to journalArticle

Adders
Thermodynamic properties
Dynamic programming
Costs
Binary decision diagrams
2008
1 Citation (Scopus)

A behavioral synthesis method with special functional units

Sadakata, T. & Matsunaga, Y., 2008, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E91-A, 4, p. 1084-1091 8 p.

Research output: Contribution to journalArticle

Clocks
Synthesis
Unit
Scheduling
Cycle
2 Citations (Scopus)

An efficient performance improvement method utilizing specialized functional units in Behavioral Synthesis

Sadakata, T. & Matsunaga, Y., 2008, 2008 Asia and South Pacific Design Automation Conference, ASP-DAC. p. 32-35 4 p. 4483969

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Clocks
Scheduling
Networks (circuits)
3 Citations (Scopus)

Area recovery under depth constraint by cut substitution for technology mapping for LUT-based FPGAs

Takata, T. & Matsunaga, Y., Aug 21 2008, 2008 Asia and South Pacific Design Automation Conference, ASP-DAC. p. 144-147 4 p. 4483928. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Field programmable gate arrays (FPGA)
Substitution reactions
Recovery
Processing
Experiments
2 Citations (Scopus)

Character projection mask set optimization for enhancing throughput of MCC projection systems

Sugihara, M., Matsunaga, Y. & Murakami, K., Jan 1 2008, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E91-A, 12, p. 3451-3460 10 p.

Research output: Contribution to journalArticle

Projection systems
Mask
Masks
Throughput
Projection
1 Citation (Scopus)

Synthesis of parallel prefix adders considering switching activities

Matsunaga, T., Kimura, S. & Matsunaga, Y., Dec 1 2008, 26th IEEE International Conference on Computer Design 2008, ICCD. p. 404-409 6 p. 4751892. (26th IEEE International Conference on Computer Design 2008, ICCD).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Adders
Thermodynamic properties
Dynamic programming
Costs
Experiments
2007
11 Citations (Scopus)

Area minimization algorithm for parallel prefix adders under bitwise delay constraints

Matsunaga, T. & Matsunaga, Y., 2007, GLSVLSI'07: Proceedings of the 2007 ACM Great Lakes Symposium on VLSI. p. 435-440 6 p. 1228886

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Adders
Dynamic programming
4 Citations (Scopus)
Scheduling
Module
Unit
Heuristic algorithms
Clocks
VLSI Design

Special section on selected papers from the 19th workshop on circuits and systems in Karuizawa

Matsunaga, Y., Miyata, T., Takenaka, T., Obote, S., Taoka, S., Yuminaka, Y., Kitajima, H., Hashimoto, T., Suzuki, N., Souda, M., Ichige, K., Fujiyoshi, M., Ohmura, M., Komatsu, S., Ohsawa, S. & Kawabe, Y., Jan 1 2007, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E90-A, 4, p. 705-706 2 p.

Research output: Contribution to journalEditorial

4 Citations (Scopus)

Technology mapping technique for enhancing throughput of multi-column-cell systems

Sugihara, M., Matsunaga, Y. & Murakami, K., Oct 15 2007, In : Proceedings of SPIE - The International Society for Optical Engineering. 6517, PART 1, 65170Z.

Research output: Contribution to journalConference article

Electron beams
Throughput
projection
Cell
Projection
7 Citations (Scopus)

Timing-constrained area minimization algorithm for parallel prefix adders

Matsunaga, T. & Matsunaga, Y., Jan 1 2007, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E90-A, 12, p. 2770-2777 8 p.

Research output: Contribution to journalArticle

Adders
Prefix
Dynamic programming
Timing
Dynamic Programming
2006
11 Citations (Scopus)

A character size optimization technique for throughput enhancement of character projection lithography

Sugihara, M., Takata, T., Nakamura, K., Inanami, R., Hayashi, H., Kishimoto, K., Hasebe, T., Kawano, Y., Matsunaga, Y., Murakam, K. & Okumura, K., Dec 1 2006, ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings. p. 2561-2564 4 p. 1693146. (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Lithography
Throughput
Photomasks
Masks
Electron beams
8 Citations (Scopus)

A CP mask development methodology for MCC systems

Sugihara, M., Takata, T., Nakamura, K., Matsunaga, Y. & Murakami, K., Sep 4 2006, In : Proceedings of SPIE - The International Society for Optical Engineering. 6283 II, 62833J.

Research output: Contribution to journalConference article

Mask
Masks
masks
projection
Projection
23 Citations (Scopus)

Cell library development methodology for throughput enhancement of character projection equipment

Sugihara, M., Takata, T., Nakamura, K., Inanami, R., Hayashi, H., Kishimoto, K., Hasebe, T., Kawano, Y., Matsunaga, Y., Murakami, K. & Okumura, K., Jan 1 2006, In : IEICE Transactions on Electronics. E89-C, 3, p. 377-383 7 p.

Research output: Contribution to journalArticle

Electron beams
Throughput
Time delay
Linear programming
Deterioration
8 Citations (Scopus)

CP mask optimization for enhancing the throughput of MCC systems

Sugihara, M., Nakamura, K., Matsunaga, Y. & Murakami, K., Dec 1 2006, Photomask Technology 2006. 63494B. (Proceedings of SPIE - The International Society for Optical Engineering; vol. 6349 I).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Mask
Masks
Throughput
masks
projection

Development of practical ATPG tool with flexible interface

Yoshimura, M. & Matsunaga, Y., Dec 1 2006, Proceedings of the 15th Asian Test Symposium 2006. 1 p. 4030755. (Proceedings of the Asian Test Symposium; vol. 2006).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Program processors
Networks (circuits)
Compaction
Combinatorial circuits
Processing

Message from Technical Program Committee

Onodera, H. & Matsunaga, Y., 2006, In : Unknown Journal. 2006, 1594623.

Research output: Contribution to journalEditorial

10 Citations (Scopus)

Technology mapping technique for throughput enhancement of character projection equipment

Sugihara, M., Takata, T., Nakamura, K., Inanami, R., Hayashi, H., Kishimoto, K., Hasebe, T., Kawano, Y., Matsunaga, Y., Murakami, K. & Okumura, K., Jul 10 2006, Emerging Lithographic Technologies X. 61510Z. (Proceedings of SPIE - The International Society for Optical Engineering; vol. 6151 I).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

shot
Throughput
Enhancement
projection
Projection
2005
10 Citations (Scopus)

Cell library development methodology for throughput enhancement of electron beam direct-write lithography systems

Sugihara, M., Takata, T., Nakamura, K., Inanami, R., Hayashi, H., Kishimoto, K., Hasebe, T., Kawano, Y., Matsunaga, Y., Murakami, K. & Okumura, K., Dec 1 2005, 2005 International Symposium on System-on-Chip, Proceedings. p. 137-140 4 p. 1595663. (2005 International Symposium on System-on-Chip, Proceedings; vol. 2005).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Lithography
Electron beams
Throughput
Time delay
Linear programming

Special section on papers selected from 2004 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2004)

Kikuchi, H., Asano, K., Fujisaka, H., Habuchi, H., Hariyama, M., Horita, E., Itoh, Y., Konishi, K., Matsunaga, Y., Murayama, T., Nakachi, T., Nakano, K., Nakashizuka, M., Natsume, K., Nishio, Y., Nishikawa, K., Ohta, A., Ozawa, S., Suzuki, M., Taguchi, A. & 5 others, Taoka, S., Yamaguchi, R., Yamazato, T., Abe, M. & Sasaki, S., Jan 1 2005, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E88-A, 6, 1 p.

Research output: Contribution to journalEditorial

2004
9 Citations (Scopus)

Enhancing the performance of multi-cycle path analysis in an industrial setting

Higuchi, H. & Matsunaga, Y., Jun 1 2004, p. 192-197. 6 p.

Research output: Contribution to conferencePaper

Product design
Sequential circuits
1 Citation (Scopus)

Practical test architecture optimization for system-on-a-chip under floorplanning constraints

Sugihara, M., Murakami, K. & Matsunaga, Y., Sep 24 2004, Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design. Smailagic, A. & Bayoumi, M. (eds.). p. 179-184 6 p. (Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Scheduling
Hardware
Testing

Test architecture optimization for system-on-a-chip under floorplanning constraints

Sugihara, M., Murakami, K. & Matsunaga, Y., Jan 1 2004, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E87-A, 12, p. 3174-3184 11 p.

Research output: Contribution to journalArticle

Floorplanning
Chip
Optimization
Locality
Wire
2002
2 Citations (Scopus)
Binary decision diagrams
Decision Diagrams
Disjoint
Efficient Algorithms
Binary
5 Citations (Scopus)

The Statistical Longest Path Problem and its Application to Delay Analysis of Logical Circuits

Ando, E., Yamashita, M., Nakata, T. & Matsunaga, Y., Jan 1 2002, ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems. Association for Computing Machinery (ACM), p. 134-139 6 p. (ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Normal distribution
Distribution functions
Networks (circuits)
Random variables
Experiments
2000

Robust heuristics for multi-level logic simplification considering local circuit structure

Zhu, Q., Matsunaga, Y., Kimura, S. & Watanabe, K., Dec 1 2000, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E83-A, 12, p. 2520-2527 8 p.

Research output: Contribution to journalArticle

Simplification
Heuristics
Logic
Data storage equipment
Combinatorial circuits
1998
3 Citations (Scopus)
Pattern matching
method