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Research Output 1986 2019

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Conference contribution
2019

An Efficient SAT-Attack Algorithm Against Logic Encryption

Matsunaga, Y. & Yoshimura, M., Jul 2019, 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design, IOLTS 2019. Gizopoulos, D., Alexandrescu, D., Papavramidou, P. & Maniatakos, M. (eds.). Institute of Electrical and Electronics Engineers Inc., p. 44-47 4 p. 8854466. (2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design, IOLTS 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Cryptography
Program processors
Networks (circuits)
Experiments
2015
6 Citations (Scopus)

Accelerating SAT-based Boolean matching for heterogeneous FPGAs using one-hot encoding and CEGAR technique

Matsunaga, Y., Mar 11 2015, 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015. Institute of Electrical and Electronics Engineers Inc., p. 255-260 6 p. 7059014. (20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Field Programmable Gate Array
Program processors
Counterexample
Field programmable gate arrays (FPGA)
Encoding
2014
3 Citations (Scopus)

Synthesis algorithm of parallel index generation units

Matsunaga, Y., 2014, Proceedings - Design, Automation and Test in Europe, DATE 2014. Institute of Electrical and Electronics Engineers Inc., 6800511

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hardware
2012
6 Citations (Scopus)

Neutron-induced soft error rate estimation for SRAM using PHITS

Yoshimoto, S., Amashita, T., Yoshimura, M., Matsunaga, Y., Yasuura, H., Izumi, S., Kawaguchi, H. & Yoshimoto, M., Nov 22 2012, Proceedings of the 2012 IEEE 18th International On-Line Testing Symposium, IOLTS 2012. p. 138-141 4 p. 6313859. (Proceedings of the 2012 IEEE 18th International On-Line Testing Symposium, IOLTS 2012).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Static random access storage
Neutrons
Data storage equipment
2011
3 Citations (Scopus)

A robust algorithm for pessimistic analysis of logic masking effects in combinational circuits

Takata, T. & Matsunaga, Y., Sep 19 2011, Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011. p. 246-251 6 p. 5994537

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Combinatorial circuits
Networks (circuits)
Redundancy
Heuristic algorithms

A soft error tolerance estimation method for sequential circuits

Yoshimura, M., Akamine, Y. & Matsunaga, Y., Dec 1 2011, Proceedings - 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011. p. 268-276 9 p. 6104452. (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Sequential circuits
Networks (circuits)
Linear equations
10 Citations (Scopus)

Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure

Yoshimoto, S., Amashita, T., Kozuwa, D., Takata, T., Yoshimura, M., Matsunaga, Y., Yasuura, H., Kawaguchi, H. & Yoshimoto, M., Sep 19 2011, Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011. p. 151-156 6 p. 5993829. (Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Static random access storage
Transistors
Error correction
Neutrons
Simulators
11 Citations (Scopus)

Power and delay aware synthesis of multi-operand adders targeting LUT-based FPGAs

Matsunaga, T., Kimura, S. & Matsunaga, Y., Sep 19 2011, IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011. p. 217-222 6 p. 5993639. (Proceedings of the International Symposium on Low Power Electronics and Design).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Adders
Compressors
Field programmable gate arrays (FPGA)
Inductive logic programming (ILP)
Application specific integrated circuits
2010
8 Citations (Scopus)

Multi-operand adder synthesis on FPGAs using generalized parallel counters

Matsunaga, T., Kimura, S. & Matsunaga, Y., Apr 28 2010, 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010. p. 337-342 6 p. 5419871. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Adders
Field programmable gate arrays (FPGA)
Application specific integrated circuits
Hardware
2009
1 Citation (Scopus)

An efficient cut enumeration for depth-optimum technology mapping for LUT-based FPGAs

Takata, T. & Matsunaga, Y., 2009, GLSVLSI 2009 - Proceedings of the 2009 Great Lakes Symposium on VLSI. p. 351-356 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Field programmable gate arrays (FPGA)
Merging
2008
2 Citations (Scopus)

An efficient performance improvement method utilizing specialized functional units in Behavioral Synthesis

Sadakata, T. & Matsunaga, Y., 2008, 2008 Asia and South Pacific Design Automation Conference, ASP-DAC. p. 32-35 4 p. 4483969

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Clocks
Scheduling
Networks (circuits)
3 Citations (Scopus)

Area recovery under depth constraint by cut substitution for technology mapping for LUT-based FPGAs

Takata, T. & Matsunaga, Y., Aug 21 2008, 2008 Asia and South Pacific Design Automation Conference, ASP-DAC. p. 144-147 4 p. 4483928. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Field programmable gate arrays (FPGA)
Substitution reactions
Recovery
Processing
Experiments
1 Citation (Scopus)

Synthesis of parallel prefix adders considering switching activities

Matsunaga, T., Kimura, S. & Matsunaga, Y., Dec 1 2008, 26th IEEE International Conference on Computer Design 2008, ICCD. p. 404-409 6 p. 4751892. (26th IEEE International Conference on Computer Design 2008, ICCD).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Adders
Thermodynamic properties
Dynamic programming
Costs
Experiments
2007
11 Citations (Scopus)

Area minimization algorithm for parallel prefix adders under bitwise delay constraints

Matsunaga, T. & Matsunaga, Y., 2007, GLSVLSI'07: Proceedings of the 2007 ACM Great Lakes Symposium on VLSI. p. 435-440 6 p. 1228886

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Adders
Dynamic programming
2006
11 Citations (Scopus)

A character size optimization technique for throughput enhancement of character projection lithography

Sugihara, M., Takata, T., Nakamura, K., Inanami, R., Hayashi, H., Kishimoto, K., Hasebe, T., Kawano, Y., Matsunaga, Y., Murakam, K. & Okumura, K., Dec 1 2006, ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings. p. 2561-2564 4 p. 1693146. (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Lithography
Throughput
Photomasks
Masks
Electron beams
8 Citations (Scopus)

CP mask optimization for enhancing the throughput of MCC systems

Sugihara, M., Nakamura, K., Matsunaga, Y. & Murakami, K., Dec 1 2006, Photomask Technology 2006. 63494B. (Proceedings of SPIE - The International Society for Optical Engineering; vol. 6349 I).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Mask
Masks
Throughput
masks
projection

Development of practical ATPG tool with flexible interface

Yoshimura, M. & Matsunaga, Y., Dec 1 2006, Proceedings of the 15th Asian Test Symposium 2006. 1 p. 4030755. (Proceedings of the Asian Test Symposium; vol. 2006).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Program processors
Networks (circuits)
Compaction
Combinatorial circuits
Processing
10 Citations (Scopus)

Technology mapping technique for throughput enhancement of character projection equipment

Sugihara, M., Takata, T., Nakamura, K., Inanami, R., Hayashi, H., Kishimoto, K., Hasebe, T., Kawano, Y., Matsunaga, Y., Murakami, K. & Okumura, K., Jul 10 2006, Emerging Lithographic Technologies X. 61510Z. (Proceedings of SPIE - The International Society for Optical Engineering; vol. 6151 I).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

shot
Throughput
Enhancement
projection
Projection
2005
10 Citations (Scopus)

Cell library development methodology for throughput enhancement of electron beam direct-write lithography systems

Sugihara, M., Takata, T., Nakamura, K., Inanami, R., Hayashi, H., Kishimoto, K., Hasebe, T., Kawano, Y., Matsunaga, Y., Murakami, K. & Okumura, K., Dec 1 2005, 2005 International Symposium on System-on-Chip, Proceedings. p. 137-140 4 p. 1595663. (2005 International Symposium on System-on-Chip, Proceedings; vol. 2005).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Lithography
Electron beams
Throughput
Time delay
Linear programming
2004
1 Citation (Scopus)

Practical test architecture optimization for system-on-a-chip under floorplanning constraints

Sugihara, M., Murakami, K. & Matsunaga, Y., Sep 24 2004, Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design. Smailagic, A. & Bayoumi, M. (eds.). p. 179-184 6 p. (Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Scheduling
Hardware
Testing
2002
5 Citations (Scopus)

The Statistical Longest Path Problem and its Application to Delay Analysis of Logical Circuits

Ando, E., Yamashita, M., Nakata, T. & Matsunaga, Y., Jan 1 2002, ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems. Association for Computing Machinery (ACM), p. 134-139 6 p. (ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Normal distribution
Distribution functions
Networks (circuits)
Random variables
Experiments
1993
19 Citations (Scopus)

Computing the transitive closure of a state transition relation

Matsunaga, Y., McGeer, P. C. & Brayton, R. K., Jan 1 1993, Proceedings - Design Automation Conference. Publ by IEEE, p. 260-265 6 p. (Proceedings - Design Automation Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Iterative methods
Data structures
1992
9 Citations (Scopus)

Multi-level logic minimization based on minimal support and its application to the minimization of look-up table type FPGAs

Fujita, M. & Matsunaga, Y., 1992, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers. Publ by IEEE, p. 560-563 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Field programmable gate arrays (FPGA)
Combinatorial circuits
97 Citations (Scopus)

On variable ordering of binary decision diagrams for the application of multi-level logic synthesis

Fujita, M., Matsunaga, Y. & Kakuda, T., Dec 1 1992, Proc Eur Conf Des Autom. Publ by IEEE, p. 50-54 5 p. (Proc Eur Conf Des Autom).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Binary decision diagrams
Networks (circuits)
Logic Synthesis
1991
2 Citations (Scopus)

A resynthesis approach for network optimization

Chen, K. C., Matsunaga, Y., Fujita, M. & Muroga, S., Jun 1 1991, Proceedings - Design Automation Conference. Publ by IEEE, p. 458-463 6 p. (Proceedings - Design Automation Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Management information systems
Data structures
1990
3 Citations (Scopus)

Automatic and semi-automatic verification of switch-level circuits with temporal logic and binary decision diagrams

Fujita, M., Matsunaga, Y. & Kakuda, T., Dec 1 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers. Publ by IEEE, p. 38-41 4 p. (1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Binary decision diagrams
Temporal logic
Switches
Networks (circuits)
Transistors
13 Citations (Scopus)

Boolean resubstitution with permissible functions and binary decision diagrams

Sato, H., Yasue, Y., Matsunaga, Y. & Fujita, M., Dec 1 1990, 27th ACM/IEEE Design Automation Conference. Proceedings 1990. Publ by IEEE, p. 284-289 6 p. (27th ACM/IEEE Design Automation Conference. Proceedings 1990).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Binary decision diagrams
Data structures
Experiments
1 Citation (Scopus)

Boolean technology mapping for both ECL and CMOS circuits based on permissible functions and binary decision diagrams

Sato, H., Takahashi, N., Matsunaga, Y. & Fujita, M., Sep 1990, Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. Publ by IEEE, p. 286-290 5 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Binary decision diagrams
Emitter coupled logic circuits
Networks (circuits)
Redundancy
3 Citations (Scopus)

Multi-level logic minimization across latch boundaries

Matsunaga, Y., Fujita, M. & Kakuda, T., Dec 1 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers. Publ by IEEE, p. 406-409 4 p. (1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Binary decision diagrams
Sequential circuits
Flip flop circuits
Labels
Topology
1989
28 Citations (Scopus)

Multi-level logic optimization using binary decision diagrams

Matsunaga, Y. & Fujita, M., 1989, IEEE Int Conf Comput Aided Des ICCAD 89 Dig Tech Pap. Anon (ed.). Publ by IEEE, p. 556-559 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Binary decision diagrams
Program processors
Data structures
Data storage equipment
Networks (circuits)