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Research Output 1986 2019

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Article
2017

An accelerating technique for SAT-based ATPG

Matsunaga, Y., Feb 1 2017, In : IPSJ Transactions on System LSI Design Methodology. 10, p. 39-44 6 p.

Research output: Contribution to journalArticle

Automatic test pattern generation
2016
Program processors
Counterexample
Encoding
Refinement
Networks (circuits)
Compaction
Grouping
Fault
Compatibility
Efficient Algorithms
2014
4 Citations (Scopus)
Generator
Synthesis
Multi-valued Logic
Hardware
Latency
2013
10 Citations (Scopus)

An exact approach for gpc-based compressor tree synthesis

Matsunaga, T., Kimura, S. & Matsunaga, Y., Jan 1 2013, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E96-A, 12, p. 2553-2560 8 p.

Research output: Contribution to journalArticle

Compressor
Adders
Compressors
Synthesis
Inductive logic programming (ILP)
2012

An exact estimation algorithm of error propagation probability for sequential circuits

Yoshimura, M., Akamine, Y. & Matsunaga, Y., Aug 17 2012, In : IPSJ Transactions on System LSI Design Methodology. 5, p. 63-70 8 p.

Research output: Contribution to journalArticle

Sequential circuits
Flip flop circuits
Linear equations
Networks (circuits)
Integrated circuits
Combinatorial circuits
Networks (circuits)
Observability
Redundancy
2011
9 Citations (Scopus)

Multi-operand adder synthesis targeting FPGAs

Matsunaga, T., Kimura, S. & Matsunaga, Y., Jan 1 2011, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E94-A, 12, p. 2579-2586 8 p.

Research output: Contribution to journalArticle

Adders
Field Programmable Gate Array
Field programmable gate arrays (FPGA)
Synthesis
Application specific integrated circuits
2009
1 Citation (Scopus)

Area recovery under depth constraint for technology mapping for LUT-based FPGAs

Takata, T. & Matsunaga, Y., Dec 1 2009, In : IPSJ Transactions on System LSI Design Methodology. 2, p. 200-211 12 p.

Research output: Contribution to journalArticle

Heuristic algorithms
Field programmable gate arrays (FPGA)
Recovery

Binding refinement for multiplexer reduction

Kodama, S. & Matsunaga, Y., Dec 1 2009, In : IPSJ Transactions on System LSI Design Methodology. 2, p. 43-52 10 p.

Research output: Contribution to journalArticle

Tabu search
Networks (circuits)
Enumeration
Field Programmable Gate Array
Field programmable gate arrays (FPGA)
Heuristics
Merging

Framework for parallel prefix adder synthesis considering switching activities

Matsunaga, T., Kimura, S. & Matsunaga, Y., Dec 1 2009, In : IPSJ Transactions on System LSI Design Methodology. 2, p. 212-221 10 p.

Research output: Contribution to journalArticle

Adders
Thermodynamic properties
Dynamic programming
Costs
Binary decision diagrams
2008
1 Citation (Scopus)

A behavioral synthesis method with special functional units

Sadakata, T. & Matsunaga, Y., 2008, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E91-A, 4, p. 1084-1091 8 p.

Research output: Contribution to journalArticle

Clocks
Synthesis
Unit
Scheduling
Cycle
2 Citations (Scopus)

Character projection mask set optimization for enhancing throughput of MCC projection systems

Sugihara, M., Matsunaga, Y. & Murakami, K., Jan 1 2008, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E91-A, 12, p. 3451-3460 10 p.

Research output: Contribution to journalArticle

Projection systems
Mask
Masks
Throughput
Projection
2007
4 Citations (Scopus)
Scheduling
Module
Unit
Heuristic algorithms
Clocks
7 Citations (Scopus)

Timing-constrained area minimization algorithm for parallel prefix adders

Matsunaga, T. & Matsunaga, Y., Jan 1 2007, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E90-A, 12, p. 2770-2777 8 p.

Research output: Contribution to journalArticle

Adders
Prefix
Dynamic programming
Timing
Dynamic Programming
2006
23 Citations (Scopus)

Cell library development methodology for throughput enhancement of character projection equipment

Sugihara, M., Takata, T., Nakamura, K., Inanami, R., Hayashi, H., Kishimoto, K., Hasebe, T., Kawano, Y., Matsunaga, Y., Murakami, K. & Okumura, K., Jan 1 2006, In : IEICE Transactions on Electronics. E89-C, 3, p. 377-383 7 p.

Research output: Contribution to journalArticle

Electron beams
Throughput
Time delay
Linear programming
Deterioration
2004

Test architecture optimization for system-on-a-chip under floorplanning constraints

Sugihara, M., Murakami, K. & Matsunaga, Y., Jan 1 2004, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E87-A, 12, p. 3174-3184 11 p.

Research output: Contribution to journalArticle

Floorplanning
Chip
Optimization
Locality
Wire
2002
2 Citations (Scopus)
Binary decision diagrams
Decision Diagrams
Disjoint
Efficient Algorithms
Binary
2000

Robust heuristics for multi-level logic simplification considering local circuit structure

Zhu, Q., Matsunaga, Y., Kimura, S. & Watanabe, K., Dec 1 2000, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E83-A, 12, p. 2520-2527 8 p.

Research output: Contribution to journalArticle

Simplification
Heuristics
Logic
Data storage equipment
Combinatorial circuits
1997

An iterative improvement method for state minimization of incompletely specified finite state machines

Higuchi, H. & Matsunaga, Y., Jan 1 1997, In : IEICE Transactions on Information and Systems. E80-D, 10, p. 993-1000 8 p.

Research output: Contribution to journalArticle

Finite automata
Heuristic algorithms
Binary decision diagrams
Merging
Program processors
1995
3 Citations (Scopus)

New algorithm for Boolean matching utilizing structural information

Matsunaga, Y., Mar 1 1995, In : IEICE Transactions on Information and Systems. E78-D, 3, p. 219-223 5 p.

Research output: Contribution to journalArticle

Phase optimization in technology mapping

Matsunaga, Y., Dec 1 1995, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E78-A, 12, p. 1735-1741 7 p.

Research output: Contribution to journalArticle

Cost functions
Trees (mathematics)
Cost Function
Optimization
Minimise
1993
1 Citation (Scopus)

A fast test pattern generation for large scale circuits

Matsunaga, Y. & Fujita, M., Sep 1993, In : Fujitsu Scientific and Technical Journal. 29, 3, p. 305-311 7 p.

Research output: Contribution to journalArticle

Combinatorial circuits
Networks (circuits)
Refining
Controllers
29 Citations (Scopus)
Test Set
Exact Algorithms
Set Covering Problem
Binary decision diagrams
Manipulation
48 Citations (Scopus)

Variable Ordering Algorithms for Ordered Binary Decision Diagrams and Their Evaluation

Fujita, M., Fujisawa, H. & Matsunaga, Y., Jan 1 1993, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 12, 1, p. 6-12 7 p.

Research output: Contribution to journalArticle

Binary decision diagrams
Networks (circuits)
Decision trees
Program processors
Data storage equipment
5 Citations (Scopus)

Variable ordering of binary decision diagrams for multi-level logic minimization

Fujita, M. & Matsunaga, Y., Jun 1 1993, In : Fujitsu Scientific and Technical Journal. 29, 2, p. 137-145 9 p.

Research output: Contribution to journalArticle

Binary decision diagrams
Formal logic
Computer aided design
Networks (circuits)
Formal verification
1990

Logic design system with evaluation‐redesign mechanism

Maruyama, F., Kakuda, T., Matsunaga, Y., Kawato, N., Minoda, Y. & Sawada, S., Jan 1 1990, In : Electronics and Communications in Japan (Part III: Fundamental Electronic Science). 73, 5, p. 105-113 9 p.

Research output: Contribution to journalArticle

Logic design
Networks (circuits)
Specifications
1986
13 Citations (Scopus)

A Hardware Maze Router with Application to Interactive Rip-Up and Reroute

Suzuki, K., Matsunaga, Y., Tachibana, M. & Ohtsuki, T., Jan 1 1986, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 5, 4, p. 466-476 11 p.

Research output: Contribution to journalArticle

Routers
Hardware
Processing
13 Citations (Scopus)

HARDWARE MAZE ROUTER WITH APPLICATION TO INTERACTIVE RIP-UP AND REROUTE.

Suzuki, K., Matsunaga, Y., Tachibana, M. & Ohtsuki, T., Oct 1 1986, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. CAD-5, 4

Research output: Contribution to journalArticle

Routers
Hardware
Processing