0.18μm CMOS processにおける擬フィボナッチ数列を用いた低消費電力動作高速DACの開発

Translated title of the contribution: Design of low-power and high-speed DAC with pseudo Fibonacci sequence in 0.18μm CMOS process

外薗 和也, 久保川 竜太, トマル アビェシク, ポカレル ラメシュ, 金谷 晴一, 吉田 啓二

Research output: Contribution to journalArticle

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