234 scheduling of 3-2 and 2-1 eliminations for parallel image compositing using non-power-of-two number of processes

Jorji Nonaka, Kenji Ono, Masahiro Fujita

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

Binary-Swap is a parallel image compositing algorithm based on recursive vector halving and distance doubling, and works efficiently when the number of processes is exactly a power-of-two (2n). Several power-of-two converting approaches for Binary-Swap have been proposed. Among them, the Telescope method, based on the Binary Blocks algorithm, has been shown as the most promising approach. The Telescope method decomposes an entire set of processes into blocks of power-of-two size and merges the smaller blocks into larger blocks in stepwise fashion. This block merging process corresponds to the communication and computational overhead of the conversion, and since it can only merge one block per stage, it becomes inefficient as the number of binary blocks increases. In this paper, we focus on a single-stage conversion method using the 3-2 and 2-1 elimination approaches. The original scheduling method, proposed by Rabenseifner et al., is limited to an odd number of processes since it always schedules a single 3-2 elimination per conversion. Taking into consideration that the 3-2 elimination can be optimized on modern HPC systems, which can overlap the communication and computation, we propose 234 Scheduling for scheduling multiple 3-2 eliminations per conversion. The multiple 3-2 elimination scheduling enlarges the application range by enabling its use on an even number of processes. We evaluated 234 Scheduling applied to Binary-Swap on the K computer, which is a modern parallel HPC system, and confirmed its effectiveness.

Original languageEnglish
Title of host publicationProceedings of the 2015 International Conference on High Performance Computing and Simulation, HPCS 2015
EditorsVesna Zeljkovic, Waleed W. Smari
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages421-428
Number of pages8
ISBN (Electronic)9781467378123
DOIs
Publication statusPublished - Sep 2 2015
Event13th International Conference on High Performance Computing and Simulation, HPCS 2015 - Amsterdam, Netherlands
Duration: Jul 20 2015Jul 24 2015

Publication series

NameProceedings of the 2015 International Conference on High Performance Computing and Simulation, HPCS 2015

Other

Other13th International Conference on High Performance Computing and Simulation, HPCS 2015
CountryNetherlands
CityAmsterdam
Period7/20/157/24/15

All Science Journal Classification (ASJC) codes

  • Computer Networks and Communications
  • Hardware and Architecture
  • Modelling and Simulation

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