3D implemented SRAM/DRAM hybrid cache architecture for high-performance and low power consumption

Koji Inoue, Shinya Hashiguchi, Shinya Ueno, Naoto Fukumoto, Kazuaki Murakami

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

This paper introduces our research status focusing on 3D-implemented microprocessors. 3D-IC is one of the most interesting techniques to achieve high-performance, low-power VLSI systems. Stacking multiple dies makes it possible to implement microprocessor cores and large caches (or DRAM) into the same chip. Although this kind of integration has a great potential to bring a breakthrough in computer systems, its efficiency strongly depends on the characteristics of target application programs. Unfortunately, applying die stacking implementation causes performance degradation for some programs. To tackle this issue, we introduce a novel cache architecture consisting of a small but fast SRAM and a stacked large DRAM. The cache attempts to adapt to varying behavior of application programs in order to compensate for the negative impact of the die stacking approach.

Original languageEnglish
Title of host publication54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011
DOIs
Publication statusPublished - Oct 13 2011
Event54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011 - Seoul, Korea, Republic of
Duration: Aug 7 2011Aug 10 2011

Publication series

NameMidwest Symposium on Circuits and Systems
ISSN (Print)1548-3746

Other

Other54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011
CountryKorea, Republic of
CitySeoul
Period8/7/118/10/11

Fingerprint

Dynamic random access storage
Static random access storage
Electric power utilization
Application programs
Microprocessor chips
Computer systems
Degradation

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Inoue, K., Hashiguchi, S., Ueno, S., Fukumoto, N., & Murakami, K. (2011). 3D implemented SRAM/DRAM hybrid cache architecture for high-performance and low power consumption. In 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011 [6026484] (Midwest Symposium on Circuits and Systems). https://doi.org/10.1109/MWSCAS.2011.6026484

3D implemented SRAM/DRAM hybrid cache architecture for high-performance and low power consumption. / Inoue, Koji; Hashiguchi, Shinya; Ueno, Shinya; Fukumoto, Naoto; Murakami, Kazuaki.

54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011. 2011. 6026484 (Midwest Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Inoue, K, Hashiguchi, S, Ueno, S, Fukumoto, N & Murakami, K 2011, 3D implemented SRAM/DRAM hybrid cache architecture for high-performance and low power consumption. in 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011., 6026484, Midwest Symposium on Circuits and Systems, 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011, Seoul, Korea, Republic of, 8/7/11. https://doi.org/10.1109/MWSCAS.2011.6026484
Inoue K, Hashiguchi S, Ueno S, Fukumoto N, Murakami K. 3D implemented SRAM/DRAM hybrid cache architecture for high-performance and low power consumption. In 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011. 2011. 6026484. (Midwest Symposium on Circuits and Systems). https://doi.org/10.1109/MWSCAS.2011.6026484
Inoue, Koji ; Hashiguchi, Shinya ; Ueno, Shinya ; Fukumoto, Naoto ; Murakami, Kazuaki. / 3D implemented SRAM/DRAM hybrid cache architecture for high-performance and low power consumption. 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011. 2011. (Midwest Symposium on Circuits and Systems).
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