3D scaling for insulated gate bipolar transistors (IGBTs) with low V ce(sat)

K. Tsutsui, K. Kakushima, T. Hoshii, A. Nakajima, Shinichi Nishizawa, H. Wakabayashi, I. Muneta, K. Sato, T. Matsudai, W. Saito, T. Saraya, K. Itou, M. Fukui, S. Suzuki, M. Kobayashi, T. Takakura, T. Hiramoto, A. Ogura, Y. Numasawa, I. Omura & 2 others H. Ohashi, H. Iwai

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Three dimensionally (3D) scaled IGBTs that have a scaling factor of 3 (k=3) with respect to current commercial products (k=1) were fabricated for the first time. The scaling was applied to the lateral and vertical dimensions as well as the gate voltage. A significant decrease in ON resistance, - V ce(sat) reduction from 1.70 to 1.26 V - was experimentally confirmed for the 3D scaled IGBTs.

Original languageEnglish
Title of host publicationProceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017
EditorsYajie Qin, Ting-Ao Tang, Zhiliang Hong
PublisherIEEE Computer Society
Pages1137-1140
Number of pages4
ISBN (Electronic)9781509066247
DOIs
Publication statusPublished - Jan 8 2018
Event12th IEEE International Conference on Advanced Semiconductor Integrated Circuits, ASICON 2017 - Guiyang, China
Duration: Oct 25 2017Oct 28 2017

Publication series

NameProceedings of International Conference on ASIC
Volume2017-October
ISSN (Print)2162-7541
ISSN (Electronic)2162-755X

Other

Other12th IEEE International Conference on Advanced Semiconductor Integrated Circuits, ASICON 2017
CountryChina
CityGuiyang
Period10/25/1710/28/17

Fingerprint

Insulated gate bipolar transistors (IGBT)
Electric potential

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Tsutsui, K., Kakushima, K., Hoshii, T., Nakajima, A., Nishizawa, S., Wakabayashi, H., ... Iwai, H. (2018). 3D scaling for insulated gate bipolar transistors (IGBTs) with low V ce(sat) In Y. Qin, T-A. Tang, & Z. Hong (Eds.), Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017 (pp. 1137-1140). (Proceedings of International Conference on ASIC; Vol. 2017-October). IEEE Computer Society. https://doi.org/10.1109/ASICON.2017.8252681

3D scaling for insulated gate bipolar transistors (IGBTs) with low V ce(sat) . / Tsutsui, K.; Kakushima, K.; Hoshii, T.; Nakajima, A.; Nishizawa, Shinichi; Wakabayashi, H.; Muneta, I.; Sato, K.; Matsudai, T.; Saito, W.; Saraya, T.; Itou, K.; Fukui, M.; Suzuki, S.; Kobayashi, M.; Takakura, T.; Hiramoto, T.; Ogura, A.; Numasawa, Y.; Omura, I.; Ohashi, H.; Iwai, H.

Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017. ed. / Yajie Qin; Ting-Ao Tang; Zhiliang Hong. IEEE Computer Society, 2018. p. 1137-1140 (Proceedings of International Conference on ASIC; Vol. 2017-October).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Tsutsui, K, Kakushima, K, Hoshii, T, Nakajima, A, Nishizawa, S, Wakabayashi, H, Muneta, I, Sato, K, Matsudai, T, Saito, W, Saraya, T, Itou, K, Fukui, M, Suzuki, S, Kobayashi, M, Takakura, T, Hiramoto, T, Ogura, A, Numasawa, Y, Omura, I, Ohashi, H & Iwai, H 2018, 3D scaling for insulated gate bipolar transistors (IGBTs) with low V ce(sat) in Y Qin, T-A Tang & Z Hong (eds), Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017. Proceedings of International Conference on ASIC, vol. 2017-October, IEEE Computer Society, pp. 1137-1140, 12th IEEE International Conference on Advanced Semiconductor Integrated Circuits, ASICON 2017, Guiyang, China, 10/25/17. https://doi.org/10.1109/ASICON.2017.8252681
Tsutsui K, Kakushima K, Hoshii T, Nakajima A, Nishizawa S, Wakabayashi H et al. 3D scaling for insulated gate bipolar transistors (IGBTs) with low V ce(sat) In Qin Y, Tang T-A, Hong Z, editors, Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017. IEEE Computer Society. 2018. p. 1137-1140. (Proceedings of International Conference on ASIC). https://doi.org/10.1109/ASICON.2017.8252681
Tsutsui, K. ; Kakushima, K. ; Hoshii, T. ; Nakajima, A. ; Nishizawa, Shinichi ; Wakabayashi, H. ; Muneta, I. ; Sato, K. ; Matsudai, T. ; Saito, W. ; Saraya, T. ; Itou, K. ; Fukui, M. ; Suzuki, S. ; Kobayashi, M. ; Takakura, T. ; Hiramoto, T. ; Ogura, A. ; Numasawa, Y. ; Omura, I. ; Ohashi, H. ; Iwai, H. / 3D scaling for insulated gate bipolar transistors (IGBTs) with low V ce(sat) Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017. editor / Yajie Qin ; Ting-Ao Tang ; Zhiliang Hong. IEEE Computer Society, 2018. pp. 1137-1140 (Proceedings of International Conference on ASIC).
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