We fabricated a 10-Gbit/s burst-mode clock and data recovery IC with a CMOS process for future high-speed access networks. Key technologies of our circuit are an input buffer amplifier that offers capacitive coupling at the input port and a new bit gating circuit that improves the duty-cycle variation tolerance of the clock recovery circuit. Our fabricated IC test board achieved error-free operations for the continuous and the asynchronous-packet signals. In the burst mode, the measured number of minimum preamble bits was less than 16 and the receivable duty-cycle variation range was 44 to over 59%. A power consumption was 1.2 W.
|Translated title of the contribution||A 10-Gbit/s CMOS Burst-Mode Clock and Data Recovery IC for High-Speed Access Networks|
|Number of pages||6|
|Journal||IEICE technical report|
|Publication status||Published - Jan 11 2005|