高速アクセス用10Gbit/s CMOSバーストモードクロックデータ再生IC

Translated title of the contribution: A 10-Gbit/s CMOS Burst-Mode Clock and Data Recovery IC for High-Speed Access Networks

木村 俊二, 野河 正史, 西村 和好, 吉田 智暁, 雲崎 清美, 西原 晋, 大友 祐輔

Research output: Contribution to journalArticle

Abstract

We fabricated a 10-Gbit/s burst-mode clock and data recovery IC with a CMOS process for future high-speed access networks. Key technologies of our circuit are an input buffer amplifier that offers capacitive coupling at the input port and a new bit gating circuit that improves the duty-cycle variation tolerance of the clock recovery circuit. Our fabricated IC test board achieved error-free operations for the continuous and the asynchronous-packet signals. In the burst mode, the measured number of minimum preamble bits was less than 16 and the receivable duty-cycle variation range was 44 to over 59%. A power consumption was 1.2 W.
Translated title of the contributionA 10-Gbit/s CMOS Burst-Mode Clock and Data Recovery IC for High-Speed Access Networks
Original languageJapanese
Pages (from-to)65-70
Number of pages6
JournalIEICE technical report
Volume104
Issue number552
Publication statusPublished - Jan 11 2005

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