0.13μm CMOSを用いた10Gb/sバースト対応CDR IC

Translated title of the contribution: A 10-Gb/s Burst-Mode CDR IC in 0.13-μm CMOS

野河 正史, 西村 和好, 木村 俊二, 吉田 智暁, 川村 智明, 富樫 稔, 雲崎 清美, 大友 祐輔

Research output: Contribution to journalArticle

Abstract

A 10-Gb/s burst-mode CDR IC was fabricated in a 0.13-μm CMOS process for the high-speed packet-based networks of the future. The input amplifier employs a data-edge detection technique to enable instantaneous amplification from the first bit of each packet and AC-coupled input without a reset signal. The CDR core uses a gated VCO to enable instantaneous phase synchronization and clock extraction for burst data. Measurement results showed that the CDR IC operates at a data rate of 10Gb/s for burst and PRBS data with no error and recovers the clock and data in less than 5 UI (0.5ns) for burst data. This means that the burst-mode CDR IC is eight times faster than previous designs and can reduce a preamble time to less than one tenth the time for previous ones.
Translated title of the contributionA 10-Gb/s Burst-Mode CDR IC in 0.13-μm CMOS
Original languageJapanese
Pages (from-to)1-5
Number of pages5
JournalIEICE technical report
Volume105
Issue number96
Publication statusPublished - May 20 2005

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