A 10-Gb/s burst-mode clock-and-data recovery IC with frequency-adjusting dual gated VCOs

Yusuke Ohtomo, Masafumi Nogawa, Kazuyoshi Nishimura, Shunji Kimura, Tomoaki Yoshida, Tomoaki Kawamura, Minora Togashi, Kiyomi Kumozaki

Research output: Contribution to journalArticle

Abstract

A high-speed serial, 10-Gb/s, passive optical network (PON) is a good candidate for a future PON system. However, there are several issues to be solved in extending the physical speed to 10 Gb/s. The issues focused on here are not only the data rate, which is eight times higher than that of a conventional GE-PON, but also the instantaneous amplification and synchronization of AC-coupling burst-input data without a reset signal. An input amplifier with data-edge detection can both detect level-varying input due to AC-coupling and respond to the first bit of a burst packet. Another issue discussed here is tolerance to long consecutive identical digits (CIDs). A burst-mode clock-and-data recovery (CDR) using dual gated VCOs (G-VCOs) is designed for 10-Gb/s operation. The relation between the frequency difference of the dual G-VCOs and CID tolerance is derived with a frequency tunable G-VCO circuit. The burst-mode CDR IC is implemented in a 0.13-μm CMOS process. It successfully operates at a data rate of 10.3125 Gb/s. The CDR IC using the edge-detection input amplifier and the G-VCO CDR core achieves amplification and synchronization in 0.2 ns with AC-coupling without a reset signal. The IC also demonstrates 1001 bits of CID tolerance, which is more than enough tolerance for 65-bit CIDs in the 64B/66B code of 10 Gigabit Ethernet. Measured data suggest that dual G-VCOs on a die have over a 20-MHz frequency difference and that the frequency adjusting between the G-VCOs is effective for increasing CID tolerance.

Original languageEnglish
Pages (from-to)903-910
Number of pages8
JournalIEICE Transactions on Electronics
VolumeE91-C
Issue number6
DOIs
Publication statusPublished - Jun 2008
Externally publishedYes

Fingerprint

Variable frequency oscillators
Clocks
Recovery
Passive optical networks
Edge detection
Amplification
Synchronization
Ethernet
Networks (circuits)

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

A 10-Gb/s burst-mode clock-and-data recovery IC with frequency-adjusting dual gated VCOs. / Ohtomo, Yusuke; Nogawa, Masafumi; Nishimura, Kazuyoshi; Kimura, Shunji; Yoshida, Tomoaki; Kawamura, Tomoaki; Togashi, Minora; Kumozaki, Kiyomi.

In: IEICE Transactions on Electronics, Vol. E91-C, No. 6, 06.2008, p. 903-910.

Research output: Contribution to journalArticle

Ohtomo, Y, Nogawa, M, Nishimura, K, Kimura, S, Yoshida, T, Kawamura, T, Togashi, M & Kumozaki, K 2008, 'A 10-Gb/s burst-mode clock-and-data recovery IC with frequency-adjusting dual gated VCOs', IEICE Transactions on Electronics, vol. E91-C, no. 6, pp. 903-910. https://doi.org/10.1093/ietele/e91-c.6.903
Ohtomo, Yusuke ; Nogawa, Masafumi ; Nishimura, Kazuyoshi ; Kimura, Shunji ; Yoshida, Tomoaki ; Kawamura, Tomoaki ; Togashi, Minora ; Kumozaki, Kiyomi. / A 10-Gb/s burst-mode clock-and-data recovery IC with frequency-adjusting dual gated VCOs. In: IEICE Transactions on Electronics. 2008 ; Vol. E91-C, No. 6. pp. 903-910.
@article{a2b7e96460424791a4446c8c8e109e63,
title = "A 10-Gb/s burst-mode clock-and-data recovery IC with frequency-adjusting dual gated VCOs",
abstract = "A high-speed serial, 10-Gb/s, passive optical network (PON) is a good candidate for a future PON system. However, there are several issues to be solved in extending the physical speed to 10 Gb/s. The issues focused on here are not only the data rate, which is eight times higher than that of a conventional GE-PON, but also the instantaneous amplification and synchronization of AC-coupling burst-input data without a reset signal. An input amplifier with data-edge detection can both detect level-varying input due to AC-coupling and respond to the first bit of a burst packet. Another issue discussed here is tolerance to long consecutive identical digits (CIDs). A burst-mode clock-and-data recovery (CDR) using dual gated VCOs (G-VCOs) is designed for 10-Gb/s operation. The relation between the frequency difference of the dual G-VCOs and CID tolerance is derived with a frequency tunable G-VCO circuit. The burst-mode CDR IC is implemented in a 0.13-μm CMOS process. It successfully operates at a data rate of 10.3125 Gb/s. The CDR IC using the edge-detection input amplifier and the G-VCO CDR core achieves amplification and synchronization in 0.2 ns with AC-coupling without a reset signal. The IC also demonstrates 1001 bits of CID tolerance, which is more than enough tolerance for 65-bit CIDs in the 64B/66B code of 10 Gigabit Ethernet. Measured data suggest that dual G-VCOs on a die have over a 20-MHz frequency difference and that the frequency adjusting between the G-VCOs is effective for increasing CID tolerance.",
author = "Yusuke Ohtomo and Masafumi Nogawa and Kazuyoshi Nishimura and Shunji Kimura and Tomoaki Yoshida and Tomoaki Kawamura and Minora Togashi and Kiyomi Kumozaki",
year = "2008",
month = "6",
doi = "10.1093/ietele/e91-c.6.903",
language = "English",
volume = "E91-C",
pages = "903--910",
journal = "IEICE Transactions on Electronics",
issn = "0916-8524",
publisher = "The Institute of Electronics, Information and Communication Engineers (IEICE)",
number = "6",

}

TY - JOUR

T1 - A 10-Gb/s burst-mode clock-and-data recovery IC with frequency-adjusting dual gated VCOs

AU - Ohtomo, Yusuke

AU - Nogawa, Masafumi

AU - Nishimura, Kazuyoshi

AU - Kimura, Shunji

AU - Yoshida, Tomoaki

AU - Kawamura, Tomoaki

AU - Togashi, Minora

AU - Kumozaki, Kiyomi

PY - 2008/6

Y1 - 2008/6

N2 - A high-speed serial, 10-Gb/s, passive optical network (PON) is a good candidate for a future PON system. However, there are several issues to be solved in extending the physical speed to 10 Gb/s. The issues focused on here are not only the data rate, which is eight times higher than that of a conventional GE-PON, but also the instantaneous amplification and synchronization of AC-coupling burst-input data without a reset signal. An input amplifier with data-edge detection can both detect level-varying input due to AC-coupling and respond to the first bit of a burst packet. Another issue discussed here is tolerance to long consecutive identical digits (CIDs). A burst-mode clock-and-data recovery (CDR) using dual gated VCOs (G-VCOs) is designed for 10-Gb/s operation. The relation between the frequency difference of the dual G-VCOs and CID tolerance is derived with a frequency tunable G-VCO circuit. The burst-mode CDR IC is implemented in a 0.13-μm CMOS process. It successfully operates at a data rate of 10.3125 Gb/s. The CDR IC using the edge-detection input amplifier and the G-VCO CDR core achieves amplification and synchronization in 0.2 ns with AC-coupling without a reset signal. The IC also demonstrates 1001 bits of CID tolerance, which is more than enough tolerance for 65-bit CIDs in the 64B/66B code of 10 Gigabit Ethernet. Measured data suggest that dual G-VCOs on a die have over a 20-MHz frequency difference and that the frequency adjusting between the G-VCOs is effective for increasing CID tolerance.

AB - A high-speed serial, 10-Gb/s, passive optical network (PON) is a good candidate for a future PON system. However, there are several issues to be solved in extending the physical speed to 10 Gb/s. The issues focused on here are not only the data rate, which is eight times higher than that of a conventional GE-PON, but also the instantaneous amplification and synchronization of AC-coupling burst-input data without a reset signal. An input amplifier with data-edge detection can both detect level-varying input due to AC-coupling and respond to the first bit of a burst packet. Another issue discussed here is tolerance to long consecutive identical digits (CIDs). A burst-mode clock-and-data recovery (CDR) using dual gated VCOs (G-VCOs) is designed for 10-Gb/s operation. The relation between the frequency difference of the dual G-VCOs and CID tolerance is derived with a frequency tunable G-VCO circuit. The burst-mode CDR IC is implemented in a 0.13-μm CMOS process. It successfully operates at a data rate of 10.3125 Gb/s. The CDR IC using the edge-detection input amplifier and the G-VCO CDR core achieves amplification and synchronization in 0.2 ns with AC-coupling without a reset signal. The IC also demonstrates 1001 bits of CID tolerance, which is more than enough tolerance for 65-bit CIDs in the 64B/66B code of 10 Gigabit Ethernet. Measured data suggest that dual G-VCOs on a die have over a 20-MHz frequency difference and that the frequency adjusting between the G-VCOs is effective for increasing CID tolerance.

UR - http://www.scopus.com/inward/record.url?scp=77953492950&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77953492950&partnerID=8YFLogxK

U2 - 10.1093/ietele/e91-c.6.903

DO - 10.1093/ietele/e91-c.6.903

M3 - Article

AN - SCOPUS:77953492950

VL - E91-C

SP - 903

EP - 910

JO - IEICE Transactions on Electronics

JF - IEICE Transactions on Electronics

SN - 0916-8524

IS - 6

ER -