A 10.3 Gb/s burst-mode CDR Using a ΔΣ DAC

Jun Terada, Kazuyoshi Nishimura, Shunji Kimura, Hiroaki Katsurai, Naoto Yoshimoto, Yusuke Ohtomo

Research output: Contribution to journalArticle

26 Citations (Scopus)

Abstract

A burst-mode clock and data recovery circuit (CDR) for 10G-EPON systems is described. We propose a new architecture with a single gated voltage-controlled oscillator (GVCO), a digital frequency detector, and aDeltaSigma digital-to-analog converter (DAC). The single GVCO and detector reduce frequency error to less than 2 MHz. The \DeltaSigma DAC eliminates external devices. Moreover, the simulation results show the DAC is more tolerant to process, voltage, and temperature (PVT) variations than a conventional charge pump. We fabricated a test CDR with this architecture using the 0.25 μ m SiGe BiCMOS process. The measurement results show root-mean-square (rms) and total jitter of the recovered data of 2.4 and 14.7 ps, respectively, instantaneous locking in 1 bit, tolerance to a 160-bit sequence without transition in the data, and jitter tolerance of over 0.27 UIpp.

Original languageEnglish
Article number4684637
Pages (from-to)2921-2928
Number of pages8
JournalIEEE Journal of Solid-State Circuits
Volume43
Issue number12
DOIs
Publication statusPublished - Dec 1 2008
Externally publishedYes

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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    Terada, J., Nishimura, K., Kimura, S., Katsurai, H., Yoshimoto, N., & Ohtomo, Y. (2008). A 10.3 Gb/s burst-mode CDR Using a ΔΣ DAC. IEEE Journal of Solid-State Circuits, 43(12), 2921-2928. [4684637]. https://doi.org/10.1109/JSSC.2008.2006229