A 10.3125-Gbit/s SiGe BiCMOS burst-mode clock and data recovery circuit with 160-bit consecutive identical digit tolerance

Jun Terada, Kazuyoshi Nishimura, Minoru Togashi, Tomoaki Kawamura, Shunji Kimura, Yusuke Ohtomo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

A burst-mode clock and data recovery (CDR) circuit for 10 G-EPON OLT receivers is presented. The CDR employs a single-VCO architecutre, which increases consecutive identical digit (CID) tolerance. The developed CDR demonstrates 160-bit CID tolerance.

Original languageEnglish
Title of host publication2007 33rd European Conference and Exhibition of Optical Communication, ECOC 2007
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9783800730421
Publication statusPublished - Jan 1 2007
Externally publishedYes
Event2007 33rd European Conference and Exhibition of Optical Communication, ECOC 2007 - Berlin, Germany
Duration: Sep 16 2007Sep 20 2007

Publication series

Name2007 33rd European Conference and Exhibition of Optical Communication, ECOC 2007

Other

Other2007 33rd European Conference and Exhibition of Optical Communication, ECOC 2007
CountryGermany
CityBerlin
Period9/16/079/20/07

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All Science Journal Classification (ASJC) codes

  • Computer Networks and Communications
  • Electrical and Electronic Engineering

Cite this

Terada, J., Nishimura, K., Togashi, M., Kawamura, T., Kimura, S., & Ohtomo, Y. (2007). A 10.3125-Gbit/s SiGe BiCMOS burst-mode clock and data recovery circuit with 160-bit consecutive identical digit tolerance. In 2007 33rd European Conference and Exhibition of Optical Communication, ECOC 2007 [5758470] (2007 33rd European Conference and Exhibition of Optical Communication, ECOC 2007). Institute of Electrical and Electronics Engineers Inc..