A 10.3125-Gbit/s SiGe BiCMOS burst-mode clock and data recovery circuit with 160-bit consecutive identical digit tolerance

Jun Terada; Kazuyoshi Nishimura; Minoru Togashi; Tomoaki Kawamura; Shunji Kimura; Yusuke Ohtomo

doi:10.1049/ic:20070248

A 10.3125-Gbit/s SiGe BiCMOS burst-mode clock and data recovery circuit with 160-bit consecutive identical digit tolerance

Jun Terada, Kazuyoshi Nishimura, Minoru Togashi, Tomoaki Kawamura, Shunji Kimura, Yusuke Ohtomo

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

A burst-mode clock and data recovery (CDR) circuit for 10 G-EPON OLT receivers is presented. The CDR employs a single-VCO architecutre, which increases consecutive identical digit (CID) tolerance. The developed CDR demonstrates 160-bit CID tolerance.

Original language	English
Title of host publication	2007 33rd European Conference and Exhibition of Optical Communication, ECOC 2007
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9783800730421
DOIs	https://doi.org/10.1049/ic:20070248
Publication status	Published - 2007
Externally published	Yes
Event	2007 33rd European Conference and Exhibition of Optical Communication, ECOC 2007 - Berlin, Germany Duration: Sept 16 2007 → Sept 20 2007

Publication series

Name	2007 33rd European Conference and Exhibition of Optical Communication, ECOC 2007

Other

Other	2007 33rd European Conference and Exhibition of Optical Communication, ECOC 2007
Country/Territory	Germany
City	Berlin
Period	9/16/07 → 9/20/07

All Science Journal Classification (ASJC) codes

Computer Networks and Communications
Electrical and Electronic Engineering

Access to Document

10.1049/ic:20070248

Cite this

Terada, J., Nishimura, K., Togashi, M., Kawamura, T., Kimura, S., & Ohtomo, Y. (2007). A 10.3125-Gbit/s SiGe BiCMOS burst-mode clock and data recovery circuit with 160-bit consecutive identical digit tolerance. In 2007 33rd European Conference and Exhibition of Optical Communication, ECOC 2007 [5758470] (2007 33rd European Conference and Exhibition of Optical Communication, ECOC 2007). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1049/ic:20070248

A 10.3125-Gbit/s SiGe BiCMOS burst-mode clock and data recovery circuit with 160-bit consecutive identical digit tolerance. / Terada, Jun; Nishimura, Kazuyoshi; Togashi, Minoru et al.

2007 33rd European Conference and Exhibition of Optical Communication, ECOC 2007. Institute of Electrical and Electronics Engineers Inc., 2007. 5758470 (2007 33rd European Conference and Exhibition of Optical Communication, ECOC 2007).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Terada, J, Nishimura, K, Togashi, M, Kawamura, T, Kimura, S & Ohtomo, Y 2007, A 10.3125-Gbit/s SiGe BiCMOS burst-mode clock and data recovery circuit with 160-bit consecutive identical digit tolerance. in 2007 33rd European Conference and Exhibition of Optical Communication, ECOC 2007., 5758470, 2007 33rd European Conference and Exhibition of Optical Communication, ECOC 2007, Institute of Electrical and Electronics Engineers Inc., 2007 33rd European Conference and Exhibition of Optical Communication, ECOC 2007, Berlin, Germany, 9/16/07. https://doi.org/10.1049/ic:20070248

Terada J, Nishimura K, Togashi M, Kawamura T, Kimura S, Ohtomo Y. A 10.3125-Gbit/s SiGe BiCMOS burst-mode clock and data recovery circuit with 160-bit consecutive identical digit tolerance. In 2007 33rd European Conference and Exhibition of Optical Communication, ECOC 2007. Institute of Electrical and Electronics Engineers Inc. 2007. 5758470. (2007 33rd European Conference and Exhibition of Optical Communication, ECOC 2007). doi: 10.1049/ic:20070248

Terada, Jun ; Nishimura, Kazuyoshi ; Togashi, Minoru et al. / A 10.3125-Gbit/s SiGe BiCMOS burst-mode clock and data recovery circuit with 160-bit consecutive identical digit tolerance. 2007 33rd European Conference and Exhibition of Optical Communication, ECOC 2007. Institute of Electrical and Electronics Engineers Inc., 2007. (2007 33rd European Conference and Exhibition of Optical Communication, ECOC 2007).

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abstract = "A burst-mode clock and data recovery (CDR) circuit for 10 G-EPON OLT receivers is presented. The CDR employs a single-VCO architecutre, which increases consecutive identical digit (CID) tolerance. The developed CDR demonstrates 160-bit CID tolerance.",

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A 10.3125-Gbit/s SiGe BiCMOS burst-mode clock and data recovery circuit with 160-bit consecutive identical digit tolerance

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