A 10.3125Gb/s burst-mode CDR circuit using a δσ DAC

Jun Terada, Kazuyoshi Nishimura, Shunji Kimura, Hiroaki Katsurai, Naoto Yoshimoto, Yusuke Ohtomo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

26 Citations (Scopus)

Abstract

A 10.3125Gb/s burst-mode CDR circuit is designed for 10G-EPON systems. A single gated VCO and ΔΣ modulator reduce frequency error to less than 2MHz and eliminate external devices. The CDR circuit achieves instantaneous locking in 1b, can tolerate a 160b sequence without transitions in the data, and has a jitter tolerance of over 0.27 Ulpp.

Original languageEnglish
Title of host publication2008 IEEE International Solid State Circuits Conference - Digest of Technical Papers, ISSCC
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages226-228
Number of pages3
ISBN (Print)9781424420100
DOIs
Publication statusPublished - 2008
Externally publishedYes
Event2008 IEEE International Solid State Circuits Conference, ISSCC - San Francisco, CA, United States
Duration: Feb 3 2008Feb 7 2008

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume51
ISSN (Print)0193-6530

Conference

Conference2008 IEEE International Solid State Circuits Conference, ISSCC
CountryUnited States
CitySan Francisco, CA
Period2/3/082/7/08

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'A 10.3125Gb/s burst-mode CDR circuit using a δσ DAC'. Together they form a unique fingerprint.

Cite this