A 10.3125Gb/s burst-mode CDR circuit using a δσ DAC

Jun Terada, Kazuyoshi Nishimura, Shunji Kimura, Hiroaki Katsurai, Naoto Yoshimoto, Yusuke Ohtomo

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

26 Citations (Scopus)

Abstract

A 10.3125Gb/s burst-mode CDR circuit is designed for 10G-EPON systems. A single gated VCO and ΔΣ modulator reduce frequency error to less than 2MHz and eliminate external devices. The CDR circuit achieves instantaneous locking in 1b, can tolerate a 160b sequence without transitions in the data, and has a jitter tolerance of over 0.27 Ulpp.

Original languageEnglish
Title of host publication2008 IEEE International Solid State Circuits Conference - Digest of Technical Papers, ISSCC
Pages226-227+609+219
DOIs
Publication statusPublished - Aug 21 2008
Externally publishedYes
Event2008 IEEE International Solid State Circuits Conference, ISSCC - San Francisco, CA, United States
Duration: Feb 3 2008 → Feb 7 2008

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume51
ISSN (Print)0193-6530

Conference

Conference2008 IEEE International Solid State Circuits Conference, ISSCC
CountryUnited States
CitySan Francisco, CA
Period2/3/08 → 2/7/08

Fingerprint

Clock and data recovery circuits (CDR circuits)
Variable frequency oscillators
Jitter
Modulators

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Terada, J., Nishimura, K., Kimura, S., Katsurai, H., Yoshimoto, N., & Ohtomo, Y. (2008). A 10.3125Gb/s burst-mode CDR circuit using a δσ DAC. In 2008 IEEE International Solid State Circuits Conference - Digest of Technical Papers, ISSCC (pp. 226-227+609+219). [4523139] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 51). https://doi.org/10.1109/ISSCC.2008.4523139

A 10.3125Gb/s burst-mode CDR circuit using a δσ DAC. / Terada, Jun; Nishimura, Kazuyoshi; Kimura, Shunji; Katsurai, Hiroaki; Yoshimoto, Naoto; Ohtomo, Yusuke.

2008 IEEE International Solid State Circuits Conference - Digest of Technical Papers, ISSCC. 2008. p. 226-227+609+219 4523139 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 51).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Terada, J, Nishimura, K, Kimura, S, Katsurai, H, Yoshimoto, N & Ohtomo, Y 2008, A 10.3125Gb/s burst-mode CDR circuit using a δσ DAC. in 2008 IEEE International Solid State Circuits Conference - Digest of Technical Papers, ISSCC., 4523139, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, vol. 51, pp. 226-227+609+219, 2008 IEEE International Solid State Circuits Conference, ISSCC, San Francisco, CA, United States, 2/3/08. https://doi.org/10.1109/ISSCC.2008.4523139
Terada J, Nishimura K, Kimura S, Katsurai H, Yoshimoto N, Ohtomo Y. A 10.3125Gb/s burst-mode CDR circuit using a δσ DAC. In 2008 IEEE International Solid State Circuits Conference - Digest of Technical Papers, ISSCC. 2008. p. 226-227+609+219. 4523139. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). https://doi.org/10.1109/ISSCC.2008.4523139
Terada, Jun ; Nishimura, Kazuyoshi ; Kimura, Shunji ; Katsurai, Hiroaki ; Yoshimoto, Naoto ; Ohtomo, Yusuke. / A 10.3125Gb/s burst-mode CDR circuit using a δσ DAC. 2008 IEEE International Solid State Circuits Conference - Digest of Technical Papers, ISSCC. 2008. pp. 226-227+609+219 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).
@inproceedings{2c333fb6bf304f68a7b631e8754be87b,
title = "A 10.3125Gb/s burst-mode CDR circuit using a δσ DAC",
abstract = "A 10.3125Gb/s burst-mode CDR circuit is designed for 10G-EPON systems. A single gated VCO and ΔΣ modulator reduce frequency error to less than 2MHz and eliminate external devices. The CDR circuit achieves instantaneous locking in 1b, can tolerate a 160b sequence without transitions in the data, and has a jitter tolerance of over 0.27 Ulpp.",
author = "Jun Terada and Kazuyoshi Nishimura and Shunji Kimura and Hiroaki Katsurai and Naoto Yoshimoto and Yusuke Ohtomo",
year = "2008",
month = "8",
day = "21",
doi = "10.1109/ISSCC.2008.4523139",
language = "English",
isbn = "9781424420100",
series = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",
pages = "226--227+609+219",
booktitle = "2008 IEEE International Solid State Circuits Conference - Digest of Technical Papers, ISSCC",

}

TY - GEN

T1 - A 10.3125Gb/s burst-mode CDR circuit using a δσ DAC

AU - Terada, Jun

AU - Nishimura, Kazuyoshi

AU - Kimura, Shunji

AU - Katsurai, Hiroaki

AU - Yoshimoto, Naoto

AU - Ohtomo, Yusuke

PY - 2008/8/21

Y1 - 2008/8/21

N2 - A 10.3125Gb/s burst-mode CDR circuit is designed for 10G-EPON systems. A single gated VCO and ΔΣ modulator reduce frequency error to less than 2MHz and eliminate external devices. The CDR circuit achieves instantaneous locking in 1b, can tolerate a 160b sequence without transitions in the data, and has a jitter tolerance of over 0.27 Ulpp.

AB - A 10.3125Gb/s burst-mode CDR circuit is designed for 10G-EPON systems. A single gated VCO and ΔΣ modulator reduce frequency error to less than 2MHz and eliminate external devices. The CDR circuit achieves instantaneous locking in 1b, can tolerate a 160b sequence without transitions in the data, and has a jitter tolerance of over 0.27 Ulpp.

UR - http://www.scopus.com/inward/record.url?scp=49549084402&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=49549084402&partnerID=8YFLogxK

U2 - 10.1109/ISSCC.2008.4523139

DO - 10.1109/ISSCC.2008.4523139

M3 - Conference contribution

AN - SCOPUS:49549084402

SN - 9781424420100

T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

SP - 226-227+609+219

BT - 2008 IEEE International Solid State Circuits Conference - Digest of Technical Papers, ISSCC

ER -

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