TY - GEN
T1 - A 10.3125Gb/s burst-mode CDR circuit using a δσ DAC
AU - Terada, Jun
AU - Nishimura, Kazuyoshi
AU - Kimura, Shunji
AU - Katsurai, Hiroaki
AU - Yoshimoto, Naoto
AU - Ohtomo, Yusuke
PY - 2008
Y1 - 2008
N2 - A 10.3125Gb/s burst-mode CDR circuit is designed for 10G-EPON systems. A single gated VCO and ΔΣ modulator reduce frequency error to less than 2MHz and eliminate external devices. The CDR circuit achieves instantaneous locking in 1b, can tolerate a 160b sequence without transitions in the data, and has a jitter tolerance of over 0.27 Ulpp.
AB - A 10.3125Gb/s burst-mode CDR circuit is designed for 10G-EPON systems. A single gated VCO and ΔΣ modulator reduce frequency error to less than 2MHz and eliminate external devices. The CDR circuit achieves instantaneous locking in 1b, can tolerate a 160b sequence without transitions in the data, and has a jitter tolerance of over 0.27 Ulpp.
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U2 - 10.1109/ISSCC.2008.4523139
DO - 10.1109/ISSCC.2008.4523139
M3 - Conference contribution
AN - SCOPUS:49549084402
SN - 9781424420100
T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
SP - 226
EP - 228
BT - 2008 IEEE International Solid State Circuits Conference - Digest of Technical Papers, ISSCC
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2008 IEEE International Solid State Circuits Conference, ISSCC
Y2 - 3 February 2008 through 7 February 2008
ER -