A 10.3125Gb/s burst-mode CDR circuit using a δσ DAC

Jun Terada; Kazuyoshi Nishimura; Shunji Kimura; Hiroaki Katsurai; Naoto Yoshimoto; Yusuke Ohtomo

doi:10.1109/ISSCC.2008.4523139

A 10.3125Gb/s burst-mode CDR circuit using a δσ DAC

Jun Terada, Kazuyoshi Nishimura, Shunji Kimura, Hiroaki Katsurai, Naoto Yoshimoto, Yusuke Ohtomo

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

28 Citations (Scopus)

Abstract

A 10.3125Gb/s burst-mode CDR circuit is designed for 10G-EPON systems. A single gated VCO and ΔΣ modulator reduce frequency error to less than 2MHz and eliminate external devices. The CDR circuit achieves instantaneous locking in 1b, can tolerate a 160b sequence without transitions in the data, and has a jitter tolerance of over 0.27 Ul_pp.

Original language	English
Title of host publication	2008 IEEE International Solid State Circuits Conference - Digest of Technical Papers, ISSCC
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	226-228
Number of pages	3
ISBN (Print)	9781424420100
DOIs	https://doi.org/10.1109/ISSCC.2008.4523139
Publication status	Published - 2008
Externally published	Yes
Event	2008 IEEE International Solid State Circuits Conference, ISSCC - San Francisco, CA, United States Duration: Feb 3 2008 → Feb 7 2008

Publication series

Name	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume	51
ISSN (Print)	0193-6530

Conference

Conference	2008 IEEE International Solid State Circuits Conference, ISSCC
Country/Territory	United States
City	San Francisco, CA
Period	2/3/08 → 2/7/08

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/ISSCC.2008.4523139

Cite this

Terada, J., Nishimura, K., Kimura, S., Katsurai, H., Yoshimoto, N., & Ohtomo, Y. (2008). A 10.3125Gb/s burst-mode CDR circuit using a δσ DAC. In 2008 IEEE International Solid State Circuits Conference - Digest of Technical Papers, ISSCC (pp. 226-228). [4523139] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 51). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSCC.2008.4523139

A 10.3125Gb/s burst-mode CDR circuit using a δσ DAC. / Terada, Jun; Nishimura, Kazuyoshi; Kimura, Shunji; Katsurai, Hiroaki; Yoshimoto, Naoto; Ohtomo, Yusuke.

2008 IEEE International Solid State Circuits Conference - Digest of Technical Papers, ISSCC. Institute of Electrical and Electronics Engineers Inc., 2008. p. 226-228 4523139 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 51).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Terada, J, Nishimura, K, Kimura, S, Katsurai, H, Yoshimoto, N & Ohtomo, Y 2008, A 10.3125Gb/s burst-mode CDR circuit using a δσ DAC. in 2008 IEEE International Solid State Circuits Conference - Digest of Technical Papers, ISSCC., 4523139, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, vol. 51, Institute of Electrical and Electronics Engineers Inc., pp. 226-228, 2008 IEEE International Solid State Circuits Conference, ISSCC, San Francisco, CA, United States, 2/3/08. https://doi.org/10.1109/ISSCC.2008.4523139

Terada J, Nishimura K, Kimura S, Katsurai H, Yoshimoto N, Ohtomo Y. A 10.3125Gb/s burst-mode CDR circuit using a δσ DAC. In 2008 IEEE International Solid State Circuits Conference - Digest of Technical Papers, ISSCC. Institute of Electrical and Electronics Engineers Inc. 2008. p. 226-228. 4523139. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). https://doi.org/10.1109/ISSCC.2008.4523139

Terada, Jun ; Nishimura, Kazuyoshi ; Kimura, Shunji ; Katsurai, Hiroaki ; Yoshimoto, Naoto ; Ohtomo, Yusuke. / A 10.3125Gb/s burst-mode CDR circuit using a δσ DAC. 2008 IEEE International Solid State Circuits Conference - Digest of Technical Papers, ISSCC. Institute of Electrical and Electronics Engineers Inc., 2008. pp. 226-228 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

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A 10.3125Gb/s burst-mode CDR circuit using a δσ DAC

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All Science Journal Classification (ASJC) codes

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