A 10Gb/s burst-mode adaptive gain select limiting amplifier in 0.13μm CMOS

Masafumi Nogawa; Yusuke Ohtomo; Shunji Kimura; Kazuyoshi Nishimura; Tomoaki Kawamura; Minoru Togashi

A 10Gb/s burst-mode adaptive gain select limiting amplifier in 0.13μm CMOS

Masafumi Nogawa, Yusuke Ohtomo, Shunji Kimura, Kazuyoshi Nishimura, Tomoaki Kawamura, Minoru Togashi

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A 10Gb/s burst-mode limiting amplifier is developed in a 0.13μm CMOS process. An adaptive gain-selection technique achieves a settling time of 0.8ns and a wide input dynamic range of 28dB, which is five-times wider than that of previous work at 10Gb/s.

Original language	English
Title of host publication	2006 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers
Pages	248+231
Publication status	Published - Dec 1 2006
Externally published	Yes
Event	2006 IEEE International Solid-State Circuits Conference, ISSCC - San Francisco, CA, United States Duration: Feb 6 2006 → Feb 9 2006

Publication series

Name	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
ISSN (Print)	0193-6530

Other

Other	2006 IEEE International Solid-State Circuits Conference, ISSCC
Country/Territory	United States
City	San Francisco, CA
Period	2/6/06 → 2/9/06

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

A 10Gb/s burst-mode adaptive gain select limiting amplifier in 0.13μm CMOS. / Nogawa, Masafumi; Ohtomo, Yusuke; Kimura, Shunji et al.
2006 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers. 2006. p. 248+231 1696135 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Nogawa, M, Ohtomo, Y, Kimura, S, Nishimura, K, Kawamura, T & Togashi, M 2006, A 10Gb/s burst-mode adaptive gain select limiting amplifier in 0.13μm CMOS. in 2006 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers., 1696135, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, pp. 248+231, 2006 IEEE International Solid-State Circuits Conference, ISSCC, San Francisco, CA, United States, 2/6/06.

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abstract = "A 10Gb/s burst-mode limiting amplifier is developed in a 0.13μm CMOS process. An adaptive gain-selection technique achieves a settling time of 0.8ns and a wide input dynamic range of 28dB, which is five-times wider than that of previous work at 10Gb/s.",

author = "Masafumi Nogawa and Yusuke Ohtomo and Shunji Kimura and Kazuyoshi Nishimura and Tomoaki Kawamura and Minoru Togashi",

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AU - Kawamura, Tomoaki

AU - Togashi, Minoru

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N2 - A 10Gb/s burst-mode limiting amplifier is developed in a 0.13μm CMOS process. An adaptive gain-selection technique achieves a settling time of 0.8ns and a wide input dynamic range of 28dB, which is five-times wider than that of previous work at 10Gb/s.

AB - A 10Gb/s burst-mode limiting amplifier is developed in a 0.13μm CMOS process. An adaptive gain-selection technique achieves a settling time of 0.8ns and a wide input dynamic range of 28dB, which is five-times wider than that of previous work at 10Gb/s.

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BT - 2006 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers

T2 - 2006 IEEE International Solid-State Circuits Conference, ISSCC

Y2 - 6 February 2006 through 9 February 2006

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A 10Gb/s burst-mode adaptive gain select limiting amplifier in 0.13μm CMOS

Abstract

Publication series

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All Science Journal Classification (ASJC) codes

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