A 1.2V 246μW CMOS latched comparator with neutralization technique for reducing Kickback Noise

Ghazal A. Fahmy, R. K. Pokharel, H. Kanaya, K. Yoshida

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

Abstract

A low power CMOS latched comparator has been designed in TSMC 0.18um employ neutralization technique for reducing Kickback Noise. The simulation results demonstrate that it can work at 1GHz suitable for high speed applications. Measurement results prove that the latched comparator consumes 246μW with a power supply of 1.2v at 10MHz. A simulation method for accurately determining dynamic offset in latched comparator is presented.

Original languageEnglish
Title of host publicationTENCON 2010 - 2010 IEEE Region 10 Conference
Pages1162-1165
Number of pages4
DOIs
Publication statusPublished - Dec 1 2010
Event2010 IEEE Region 10 Conference, TENCON 2010 - Fukuoka, Japan
Duration: Nov 21 2010Nov 24 2010

Publication series

NameIEEE Region 10 Annual International Conference, Proceedings/TENCON

Other

Other2010 IEEE Region 10 Conference, TENCON 2010
CountryJapan
CityFukuoka
Period11/21/1011/24/10

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Electrical and Electronic Engineering

Cite this

Fahmy, G. A., Pokharel, R. K., Kanaya, H., & Yoshida, K. (2010). A 1.2V 246μW CMOS latched comparator with neutralization technique for reducing Kickback Noise. In TENCON 2010 - 2010 IEEE Region 10 Conference (pp. 1162-1165). [5686392] (IEEE Region 10 Annual International Conference, Proceedings/TENCON). https://doi.org/10.1109/TENCON.2010.5686392