TY - GEN
T1 - A 1.2V 246μW CMOS latched comparator with neutralization technique for reducing Kickback Noise
AU - Fahmy, Ghazal A.
AU - Pokharel, R. K.
AU - Kanaya, H.
AU - Yoshida, K.
PY - 2010/12/1
Y1 - 2010/12/1
N2 - A low power CMOS latched comparator has been designed in TSMC 0.18um employ neutralization technique for reducing Kickback Noise. The simulation results demonstrate that it can work at 1GHz suitable for high speed applications. Measurement results prove that the latched comparator consumes 246μW with a power supply of 1.2v at 10MHz. A simulation method for accurately determining dynamic offset in latched comparator is presented.
AB - A low power CMOS latched comparator has been designed in TSMC 0.18um employ neutralization technique for reducing Kickback Noise. The simulation results demonstrate that it can work at 1GHz suitable for high speed applications. Measurement results prove that the latched comparator consumes 246μW with a power supply of 1.2v at 10MHz. A simulation method for accurately determining dynamic offset in latched comparator is presented.
UR - http://www.scopus.com/inward/record.url?scp=79951586441&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=79951586441&partnerID=8YFLogxK
U2 - 10.1109/TENCON.2010.5686392
DO - 10.1109/TENCON.2010.5686392
M3 - Conference contribution
AN - SCOPUS:79951586441
SN - 9781424468904
T3 - IEEE Region 10 Annual International Conference, Proceedings/TENCON
SP - 1162
EP - 1165
BT - TENCON 2010 - 2010 IEEE Region 10 Conference
T2 - 2010 IEEE Region 10 Conference, TENCON 2010
Y2 - 21 November 2010 through 24 November 2010
ER -