A 1.5 MLIPS 40-bit AI processor

Hirohisa Machida, Hideki Ando, Chikako Ikenaga, Hiroshi Nakashima, Atsushi Maeda, Masao Nakaya

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

A high-performance 40-b AI (artificial intelligence) processor with a capability of 1.5 MLIPS (mega-logical-inference per second) in append has been developed. The performance of this processor is achieved by the combination of novel architectures of pipelined data typing and dereference, a 0.8-μm CMOS technology, and a clock scheme.

Original languageEnglish
Title of host publicationProceedings of the Custom Integrated Circuits Conference
PublisherPubl by IEEE
ISBN (Print)0780300157
Publication statusPublished - Dec 1 1991
Externally publishedYes
EventProceedings of the IEEE 1991 Custom Integrated Circuits Conference - San Diego, CA, USA
Duration: May 12 1991May 15 1991

Publication series

NameProceedings of the Custom Integrated Circuits Conference
ISSN (Print)0886-5930

Other

OtherProceedings of the IEEE 1991 Custom Integrated Circuits Conference
CitySan Diego, CA, USA
Period5/12/915/15/91

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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