TY - JOUR
T1 - A 2.4-GHz 0.18-μm CMOS Class E single-ended switching power amplifier with a self-biased cascode
AU - Zainol Murad, Sohiful Anuar
AU - Pokharel, Ramesh K.
AU - Kanaya, Haruichi
AU - Yoshida, Keiji
AU - Nizhnik, Oleg
N1 - Funding Information:
In April 2005, he joined the Department of Electronics, Graduate School of Information Science and Electrical Engineering, Kyushu University where he is currently an assistant professor. His current research interests include the employment of passive components such as CPW in RF CMOS system LSI, EMC and signal integrity issues of LSI, and low-noise and high linear RF front-end architectures. He is a member of the IEEE. Dr. Pokharel was a recipient of the Monbu-Kagakusho Scholarship of the Japanese Government (1997–2003) and an excellent COE research presentation award from the University of Tokyo in 2003.
Funding Information:
This work was partly supported by a grant of Knowledge Cluster Initiative implemented by Ministry of Education, Culture, Sports, Science and Technology (MEXT) and KAKENHI. This work was also partly supported by VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with CADENCE Corporation and Agilent Corporation.
PY - 2010/9
Y1 - 2010/9
N2 - This paper describes the design of a 2.4-GHz CMOS Class E single-ended power amplifier (PA) for WLAN applications in TSMC 0.18-μm CMOS technology. The Class E PA proposed in this paper employs cascode topology with a self-biasing technique to prevent device stress and to decrease the requirement for additional bond pads. Further, all inductors are realized by bondwires for high PA performance. The post-layout simulation results indicate that the PA delivers 23 dBm output power and 44.5% power added efficiency with 3.3 V power supply into a 50 Ω load.
AB - This paper describes the design of a 2.4-GHz CMOS Class E single-ended power amplifier (PA) for WLAN applications in TSMC 0.18-μm CMOS technology. The Class E PA proposed in this paper employs cascode topology with a self-biasing technique to prevent device stress and to decrease the requirement for additional bond pads. Further, all inductors are realized by bondwires for high PA performance. The post-layout simulation results indicate that the PA delivers 23 dBm output power and 44.5% power added efficiency with 3.3 V power supply into a 50 Ω load.
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U2 - 10.1016/j.aeue.2009.06.002
DO - 10.1016/j.aeue.2009.06.002
M3 - Article
AN - SCOPUS:77954027491
VL - 64
SP - 813
EP - 818
JO - AEU - International Journal of Electronics and Communications
JF - AEU - International Journal of Electronics and Communications
SN - 1434-8411
IS - 9
ER -