A 25-Gb/s 480-mW CMOS modulator driver using area-efficient 3D inductor peaking

Shinsuke Nakano, Masafumi Nogawa, Hideyuki Nosaka, Akira Tsuchiya, Hidetoshi Onodera, Shunji Kimura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Citations (Scopus)

Abstract

We propose a low-power and compact 25-Gb/s differential CMOS modulator driver. To achieve low power consumption, we employ an output driver with a high-gain single-stage amplifier and a gainless pre-driver with an equalizer function. In the pre-driver, we use area-efficient 3D inductors for the inductor peaking technique to obtain the equalizer function with compactness. We also employ a cascode amplifier consisting of high-voltage and standard MOSFETs to output a large voltage swing in CMOS technology. The proposed driver was fabricated in 65-nm 1P9M standard CMOS. It exhibits a data rate of 25 Gb/s, a differential output swing of 3.3 Vpp with an input swing of 300 mVpp, and power consumption of 480 mW with 1.2-/3.3-V dual supplies. The active area is only 0.029 mm2, including all inductors. The results indicate that the best power efficiency, which is 26 % better than the state of the art, and good power consumption versus output swing FoM (mW/Vpp) are achieved.

Original languageEnglish
Title of host publication2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781467371919
DOIs
Publication statusPublished - Jan 19 2016
Externally publishedYes
Event11th IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Xiamen, Fujian, China
Duration: Nov 9 2015Nov 11 2015

Publication series

Name2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings

Conference

Conference11th IEEE Asian Solid-State Circuits Conference, A-SSCC 2015
CountryChina
CityXiamen, Fujian
Period11/9/1511/11/15

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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