A 3.1-6.0 GHz CMOS UWB power amplifier with good linearity and group delay variation

R. Sapawi, Ramesh Pokharel, D. A A Mat, Haruichi Kanaya, K. Yoshida

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Citations (Scopus)

Abstract

This paper presents a design of 3.1-6.0 GHz power amplifier (PA) 0.18 μm CMOS technology for ultra-wideband (UWB) applications. The UWB PA employs two stages amplifier and inter-stage circuit to provide a wider gain and gain flatness while shunt resistive feedback technique is adopted at the input stage to provide wideband input matching. To obtain high and flat gain, good group delay variation and linearity at the same time, the inductive peaking technique and Class A PA are employed at the first stage and the second stage. The measurement results indicated that the proposed PA design has an average gain of 10±1 dB, an input return loss (S 11) less than 6 dB, an output return loss (S22) less than -7 dB, and group delay variation of ±195.5 ps are obtained across the whole band. A good input 1dB compression point of 5 dBm and input third-order intercept point of 5 dBm at 5 GHz are achieved while consuming 30 mW power from 1.8 V supply voltage.

Original languageEnglish
Title of host publicationAsia-Pacific Microwave Conference Proceedings, APMC 2011
Pages9-12
Number of pages4
Publication statusPublished - 2011
EventAsia-Pacific Microwave Conference, APMC 2011 - Melbourne, VIC, Australia
Duration: Dec 5 2011Dec 8 2011

Other

OtherAsia-Pacific Microwave Conference, APMC 2011
CountryAustralia
CityMelbourne, VIC
Period12/5/1112/8/11

Fingerprint

Broadband amplifiers
Group delay
Power amplifiers
Ultra-wideband (UWB)
Feedback
Networks (circuits)
Electric potential

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Sapawi, R., Pokharel, R., Mat, D. A. A., Kanaya, H., & Yoshida, K. (2011). A 3.1-6.0 GHz CMOS UWB power amplifier with good linearity and group delay variation. In Asia-Pacific Microwave Conference Proceedings, APMC 2011 (pp. 9-12). [6173672]

A 3.1-6.0 GHz CMOS UWB power amplifier with good linearity and group delay variation. / Sapawi, R.; Pokharel, Ramesh; Mat, D. A A; Kanaya, Haruichi; Yoshida, K.

Asia-Pacific Microwave Conference Proceedings, APMC 2011. 2011. p. 9-12 6173672.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Sapawi, R, Pokharel, R, Mat, DAA, Kanaya, H & Yoshida, K 2011, A 3.1-6.0 GHz CMOS UWB power amplifier with good linearity and group delay variation. in Asia-Pacific Microwave Conference Proceedings, APMC 2011., 6173672, pp. 9-12, Asia-Pacific Microwave Conference, APMC 2011, Melbourne, VIC, Australia, 12/5/11.
Sapawi R, Pokharel R, Mat DAA, Kanaya H, Yoshida K. A 3.1-6.0 GHz CMOS UWB power amplifier with good linearity and group delay variation. In Asia-Pacific Microwave Conference Proceedings, APMC 2011. 2011. p. 9-12. 6173672
Sapawi, R. ; Pokharel, Ramesh ; Mat, D. A A ; Kanaya, Haruichi ; Yoshida, K. / A 3.1-6.0 GHz CMOS UWB power amplifier with good linearity and group delay variation. Asia-Pacific Microwave Conference Proceedings, APMC 2011. 2011. pp. 9-12
@inproceedings{f87aadd599f04292b7feaac7e8d697c3,
title = "A 3.1-6.0 GHz CMOS UWB power amplifier with good linearity and group delay variation",
abstract = "This paper presents a design of 3.1-6.0 GHz power amplifier (PA) 0.18 μm CMOS technology for ultra-wideband (UWB) applications. The UWB PA employs two stages amplifier and inter-stage circuit to provide a wider gain and gain flatness while shunt resistive feedback technique is adopted at the input stage to provide wideband input matching. To obtain high and flat gain, good group delay variation and linearity at the same time, the inductive peaking technique and Class A PA are employed at the first stage and the second stage. The measurement results indicated that the proposed PA design has an average gain of 10±1 dB, an input return loss (S 11) less than 6 dB, an output return loss (S22) less than -7 dB, and group delay variation of ±195.5 ps are obtained across the whole band. A good input 1dB compression point of 5 dBm and input third-order intercept point of 5 dBm at 5 GHz are achieved while consuming 30 mW power from 1.8 V supply voltage.",
author = "R. Sapawi and Ramesh Pokharel and Mat, {D. A A} and Haruichi Kanaya and K. Yoshida",
year = "2011",
language = "English",
isbn = "9780858259744",
pages = "9--12",
booktitle = "Asia-Pacific Microwave Conference Proceedings, APMC 2011",

}

TY - GEN

T1 - A 3.1-6.0 GHz CMOS UWB power amplifier with good linearity and group delay variation

AU - Sapawi, R.

AU - Pokharel, Ramesh

AU - Mat, D. A A

AU - Kanaya, Haruichi

AU - Yoshida, K.

PY - 2011

Y1 - 2011

N2 - This paper presents a design of 3.1-6.0 GHz power amplifier (PA) 0.18 μm CMOS technology for ultra-wideband (UWB) applications. The UWB PA employs two stages amplifier and inter-stage circuit to provide a wider gain and gain flatness while shunt resistive feedback technique is adopted at the input stage to provide wideband input matching. To obtain high and flat gain, good group delay variation and linearity at the same time, the inductive peaking technique and Class A PA are employed at the first stage and the second stage. The measurement results indicated that the proposed PA design has an average gain of 10±1 dB, an input return loss (S 11) less than 6 dB, an output return loss (S22) less than -7 dB, and group delay variation of ±195.5 ps are obtained across the whole band. A good input 1dB compression point of 5 dBm and input third-order intercept point of 5 dBm at 5 GHz are achieved while consuming 30 mW power from 1.8 V supply voltage.

AB - This paper presents a design of 3.1-6.0 GHz power amplifier (PA) 0.18 μm CMOS technology for ultra-wideband (UWB) applications. The UWB PA employs two stages amplifier and inter-stage circuit to provide a wider gain and gain flatness while shunt resistive feedback technique is adopted at the input stage to provide wideband input matching. To obtain high and flat gain, good group delay variation and linearity at the same time, the inductive peaking technique and Class A PA are employed at the first stage and the second stage. The measurement results indicated that the proposed PA design has an average gain of 10±1 dB, an input return loss (S 11) less than 6 dB, an output return loss (S22) less than -7 dB, and group delay variation of ±195.5 ps are obtained across the whole band. A good input 1dB compression point of 5 dBm and input third-order intercept point of 5 dBm at 5 GHz are achieved while consuming 30 mW power from 1.8 V supply voltage.

UR - http://www.scopus.com/inward/record.url?scp=84860537897&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84860537897&partnerID=8YFLogxK

M3 - Conference contribution

SN - 9780858259744

SP - 9

EP - 12

BT - Asia-Pacific Microwave Conference Proceedings, APMC 2011

ER -