Abstract
This paper describes the design of 5-GHz fully integrated CMOS class-E single-ended power amplifier (PA) for wireless transmitter applications in a 0.18-μm CMOS technology. The proposed class-E PA employs the cascode topology with a self-biasing technique to reduce device stress. Three cascaded class-D driver amplifiers are used to actualize the sharp switching at the class-E power stage. All device components are integrated on chip and the chip area is 1.0×1.3 mm2. The measurement results indicate that the PA delivers 16.4 dBm output power and 35.4 % power-added efficiency with 2.3 V power supply voltage into a 50 Ω load.
| Original language | English |
|---|---|
| Title of host publication | Proceedings of the 2012 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2012 |
| Pages | 237-239 |
| Number of pages | 3 |
| DOIs | |
| Publication status | Published - 2012 |
| Event | 2012 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2012 - Singapore, Singapore Duration: Nov 21 2012 → Nov 23 2012 |
Other
| Other | 2012 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2012 |
|---|---|
| Country | Singapore |
| City | Singapore |
| Period | 11/21/12 → 11/23/12 |
Fingerprint
All Science Journal Classification (ASJC) codes
- Computer Networks and Communications
Cite this
A 5-GHz fully integrated CMOS class-E power amplifier using self-biasing technique with cascaded class-D drivers. / Yamashita, Yuki; Kanemoto, Daisuke; Kanaya, Haruichi; Pokharel, Ramesh; Yoshida, Keiji.
Proceedings of the 2012 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2012. 2012. p. 237-239 6401672.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - A 5-GHz fully integrated CMOS class-E power amplifier using self-biasing technique with cascaded class-D drivers
AU - Yamashita, Yuki
AU - Kanemoto, Daisuke
AU - Kanaya, Haruichi
AU - Pokharel, Ramesh
AU - Yoshida, Keiji
PY - 2012
Y1 - 2012
N2 - This paper describes the design of 5-GHz fully integrated CMOS class-E single-ended power amplifier (PA) for wireless transmitter applications in a 0.18-μm CMOS technology. The proposed class-E PA employs the cascode topology with a self-biasing technique to reduce device stress. Three cascaded class-D driver amplifiers are used to actualize the sharp switching at the class-E power stage. All device components are integrated on chip and the chip area is 1.0×1.3 mm2. The measurement results indicate that the PA delivers 16.4 dBm output power and 35.4 % power-added efficiency with 2.3 V power supply voltage into a 50 Ω load.
AB - This paper describes the design of 5-GHz fully integrated CMOS class-E single-ended power amplifier (PA) for wireless transmitter applications in a 0.18-μm CMOS technology. The proposed class-E PA employs the cascode topology with a self-biasing technique to reduce device stress. Three cascaded class-D driver amplifiers are used to actualize the sharp switching at the class-E power stage. All device components are integrated on chip and the chip area is 1.0×1.3 mm2. The measurement results indicate that the PA delivers 16.4 dBm output power and 35.4 % power-added efficiency with 2.3 V power supply voltage into a 50 Ω load.
UR - http://www.scopus.com/inward/record.url?scp=84873136065&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84873136065&partnerID=8YFLogxK
U2 - 10.1109/RFIT.2012.6401672
DO - 10.1109/RFIT.2012.6401672
M3 - Conference contribution
AN - SCOPUS:84873136065
SN - 9781467323048
SP - 237
EP - 239
BT - Proceedings of the 2012 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2012
ER -