A 600V deep-implanted gate vertical JFET

M. Mizukami, O. Takikawa, M. Murooka, S. Imai, K. Kinoshita, T. Hatakeyama, M. Tsukuda, W. Saito, I. Omura, T. Shinohe

Research output: Contribution to journalConference article

6 Citations (Scopus)

Abstract

A 4H-SiC 600V class Deep-Implanted gate Vertical JFET (DI-VJFET) is reported. To achieve lower on-resistance and higher blocking-voltage, the design of channel region plays an essential role. Therefore, the channel dimensions were optimized with the ISE device simulator and calculated results were compared with experimental results. Moreover, the actual channel dimensions of fabricated samples were analyzed by SSRM (Scanning Spread Resistance Microscopy) measurements. The potential distributions in on/off-state were analyzed by SPoM (Scanning Potential Microscopy) measurements. The active areas of 2.2×10-3, 1.6×10-2 [cm2] (small chip), and 5.3×10-2 [cm2] (large chip) were fabricated, in this study. The small chips were evaluated to ascertain the dependence of the electric characteristics on the design parameters. The blocking-voltages were varied up to 1100V, and the on-resistances were varied down to 7.8mΩcm2 depending on the fabricated channel opening. The DI-VJFET in this work has almost the same electric characteristics as Si Cool-MOSFET. The large chips exhibited specific on-resistance of 16mΩcm2, drain current of 5A, and blocking-voltage of 900V. The turn-off speed of the large chip was measured with resistive load circuit. The turn-off time was 200ns for external resistance of 60Ω.

Original languageEnglish
Pages (from-to)1217-1220
Number of pages4
JournalMaterials Science Forum
Volume457-460
Issue numberII
DOIs
Publication statusPublished - 2004
Externally publishedYes
EventProceedings of the 10th International Conference on Silicon Carbide and Related Materials, ICSCRM 2003 - Lyon, France
Duration: Oct 5 2003Oct 10 2003

All Science Journal Classification (ASJC) codes

  • Materials Science(all)
  • Condensed Matter Physics
  • Mechanics of Materials
  • Mechanical Engineering

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  • Cite this

    Mizukami, M., Takikawa, O., Murooka, M., Imai, S., Kinoshita, K., Hatakeyama, T., Tsukuda, M., Saito, W., Omura, I., & Shinohe, T. (2004). A 600V deep-implanted gate vertical JFET. Materials Science Forum, 457-460(II), 1217-1220. https://doi.org/10.4028/www.scientific.net/msf.457-460.1217