3進数を用いた8bitセグメント型容量DACの開発

Translated title of the contribution: A 8-bit segmented charge-redistributed DAC using ternary logic

大城 啓吾, 兼本 大輔, ラメシュ ポカレル, 金谷 晴一, 吉田 啓二

Research output: Contribution to journalArticle

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Engineering & Materials Science