Recently, progress in shrinking CMOS process technology and increasing chip size has made interconnect delay a serious problem in deep micron LSI design. The interconnect delay is maximized by the influence of crosstalk when adjacent wires simultaneously switch in opposite transient directions. This paper proposes an on-chip bus delay reduction technique based on shifting the signal transition timing of adjacent wires. From an equation for the approximate bus delay, delay reduction can be achieved by applying the proposed technique to repeater-inserted on-chip buses. The result of SPICE simulation also shows that at most a 20% reduction of the total bus delay can be achieved.
|Number of pages||8|
|Journal||Electronics and Communications in Japan, Part III: Fundamental Electronic Science (English translation of Denshi Tsushin Gakkai Ronbunshi)|
|Publication status||Published - Jan 10 2002|
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering