TY - GEN
T1 - A Capacitive Power Transfer System with a CL Network for Improved System Performance
AU - Mostafa, Tarek M.
AU - Bui, Dai
AU - Muharam, Aam
AU - Hattori, Reiji
AU - Hu, Aiguo Patrick
N1 - Publisher Copyright:
© 2018 IEEE.
PY - 2019/2/11
Y1 - 2019/2/11
N2 - This paper introduces the analysis and optimization of capacitive power transfer system with a CL compensation circuit on the secondary for reduced voltage stress across the electric field coupling interface and less system sensitivity. The system has been mathematically analyzed to understand the effect of the CL circuit. And simulation and experimental studies are also carried out for verifications. It is found by increasing Cp (and reducing Lp accordingly to be tuned to the nominal frequency), the quality factor (Q) can be reduced to make the system less sensitive to circuit parameter and load variations, thus easier to tune. However, the CL network should be carefully designed to reduce the voltage stress and electric field leakage around the interface. A practical circuit is built which has demonstrated 5 W of power transfer across a combined interface capacitance of ∼ 1 nF at an operating frequency of 1 MHz, and the system power efficiency is above 65%. The voltage stress and sensitivity reduction have been confirmed practically.
AB - This paper introduces the analysis and optimization of capacitive power transfer system with a CL compensation circuit on the secondary for reduced voltage stress across the electric field coupling interface and less system sensitivity. The system has been mathematically analyzed to understand the effect of the CL circuit. And simulation and experimental studies are also carried out for verifications. It is found by increasing Cp (and reducing Lp accordingly to be tuned to the nominal frequency), the quality factor (Q) can be reduced to make the system less sensitive to circuit parameter and load variations, thus easier to tune. However, the CL network should be carefully designed to reduce the voltage stress and electric field leakage around the interface. A practical circuit is built which has demonstrated 5 W of power transfer across a combined interface capacitance of ∼ 1 nF at an operating frequency of 1 MHz, and the system power efficiency is above 65%. The voltage stress and sensitivity reduction have been confirmed practically.
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U2 - 10.1109/WPT.2018.8639497
DO - 10.1109/WPT.2018.8639497
M3 - Conference contribution
AN - SCOPUS:85063147796
T3 - 2018 IEEE Wireless Power Transfer Conference, WPTC 2018
BT - 2018 IEEE Wireless Power Transfer Conference, WPTC 2018
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2018 IEEE Wireless Power Transfer Conference, WPTC 2018
Y2 - 3 June 2018 through 7 June 2018
ER -