A capture-safe test generation scheme for at-speed scan testing

X. Wen, K. Miyase, S. Kajihara, H. Furukawa, Y. Yamato, A. Takashima, K. Noda, H. Ito, K. Hatayama, T. Aikyo, K. K. Saluja

Research output: Chapter in Book/Report/Conference proceedingConference contribution

34 Citations (Scopus)

Abstract

Capture-safety, defined as the avoidance of any timing error due to unduly high launch switching activity in capture mode during at-speed scan testing, is critical for avoiding test-induced yield loss. Although point techniques are available for reducing capture IR-drop, there is a lack of complete capture-safe test generation flows. The paper addresses this problem by proposing a novel and practical capture-safe test generation scheme, featuring (1) reliable capture-safety checking and (2) effective capture-safety improvement by combining X-bit identification & X-filling with low launch-switching- activity test generation. This scheme is compatible with existing ATPG flows, and achieves capture-safety with no changes in the circuit-under-test or the clocking scheme.

Original languageEnglish
Title of host publicationProceedings - 13th IEEE European Test Symposium, ETS 2008
Pages55-60
Number of pages6
DOIs
Publication statusPublished - 2008
Externally publishedYes
Event13th IEEE European Test Symposium, ETS 2008 - Verbania, Italy
Duration: May 25 2008May 29 2008

Other

Other13th IEEE European Test Symposium, ETS 2008
CountryItaly
CityVerbania
Period5/25/085/29/08

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

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