Abstract
A CMOS variable voltage attenuator(VVA) with wide bandwidth has been designed and fabricated in a 0.18-μm CMOS process. Four bridge-T stages are cascaded to achieve 12 dB of dynamic range attenuation over a frequency range from DC up to 2.5 GHz. Cascaded bridge-T stages can be programmed to achieve the full scale attenuation and ensure good input and output matching. The design operates with 1.5-dB step size and with a maximum input power of -13 dBm in the entire frequency DC-2.5 GHz range. Worst case S11 is -11.5 dB across the frequency band. The design achieves an input third order intercept point (IIP3) of+31 dBm at maximum-attenuation.
Original language | English |
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Pages | 352-355 |
Number of pages | 4 |
DOIs | |
Publication status | Published - Feb 5 2015 |
Event | 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014 - Ishigaki Island, Okinawa, Japan Duration: Nov 17 2014 → Nov 20 2014 |
Other
Other | 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014 |
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Country | Japan |
City | Ishigaki Island, Okinawa |
Period | 11/17/14 → 11/20/14 |
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering