A design methodology for SAR ADC optimal redundancy bit

Toru Okazaki, Daisuke Kanemoto, Ramesh Pokharel, Keiji Yoshida, Haruichi Kanaya

Research output: Contribution to journalLetter

1 Citation (Scopus)

Abstract

This paper presents a design method of SAR ADC (Successive Approximation Register Analog-to-Digital Converter ADC) utilizing redundancy bits. In general, binary search algorithm is used as a conventional SAR ADC operation algorithm. It's possible to realize a high-speed SAR ADC by using non-binary search algorithm which is realized by adding redundancy bits. However, the A/D conversion time varies depending on the number of redundancy bits. Therefore, in order that the conversion time is the shortest, it's necessary that an appropriate amount of redundancy be added. We show a methodology of finding the appropriate number of redundancy bits.

Original languageEnglish
JournalIEICE Electronics Express
Volume11
Issue number10
DOIs
Publication statusPublished - 2014

Fingerprint

redundancy
Redundancy
methodology
registers
analog to digital converters
Digital to analog conversion
high speed
approximation

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering

Cite this

A design methodology for SAR ADC optimal redundancy bit. / Okazaki, Toru; Kanemoto, Daisuke; Pokharel, Ramesh; Yoshida, Keiji; Kanaya, Haruichi.

In: IEICE Electronics Express, Vol. 11, No. 10, 2014.

Research output: Contribution to journalLetter

Okazaki, Toru ; Kanemoto, Daisuke ; Pokharel, Ramesh ; Yoshida, Keiji ; Kanaya, Haruichi. / A design methodology for SAR ADC optimal redundancy bit. In: IEICE Electronics Express. 2014 ; Vol. 11, No. 10.
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