A design scheme for a reconfigurable accelerator implemented by single-flux quantum circuits

Farhad Mehdipour, Hiroaki Honda, Koji Inoue, Hiroshi Kataoka, Kazuaki Murakami

Research output: Contribution to journalArticle

6 Citations (Scopus)

Abstract

A large-scale reconfigurable data-path processor (LSRDP) implemented by single-flux quantum (SFQ) circuits is introduced which is integrated to a general purpose processor to accelerate data flow graphs (DFGs) extracted from scientific applications. A number of applications are discovered and analyzed throughout the LSRDP design procedure. Various design steps and particularly the DFG mapping process are discussed and our techniques for optimizing the area of accelerator will be presented as well. Different design alternatives are examined through exploring the LSRDP design space and an appropriate architecture is determined for the accelerator. Primary experiments demonstrate capability of the designed architecture to achieve performance values up to 210 Gflops for attempted applications.

Original languageEnglish
Pages (from-to)169-179
Number of pages11
JournalJournal of Systems Architecture
Volume57
Issue number1
DOIs
Publication statusPublished - Jan 1 2011

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All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture

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