A design technique for a high-speed SAR ADC using non-binary search algorithm and redundancy

Toru Okazaki, Daisuke Kanemoto, Ramesh Pokharel, Keiji Yoshida, Haruichi Kanaya

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

This paper presents a design technique of minimizing time for each bit decision and adding appropriate redundancy bits. The technique helps the design of a SAR ADC. We show that the conversion time of proposed SAR ADCs can get faster than that of conventional ones by using the technique.

Original languageEnglish
Title of host publication2013 Asia-Pacific Microwave Conference Proceedings, APMC 2013
Pages506-508
Number of pages3
DOIs
Publication statusPublished - Dec 1 2013
Event2013 3rd Asia-Pacific Microwave Conference, APMC 2013 - Seoul, Korea, Republic of
Duration: Nov 5 2013Nov 8 2013

Publication series

NameAsia-Pacific Microwave Conference Proceedings, APMC

Other

Other2013 3rd Asia-Pacific Microwave Conference, APMC 2013
CountryKorea, Republic of
CitySeoul
Period11/5/1311/8/13

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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  • Cite this

    Okazaki, T., Kanemoto, D., Pokharel, R., Yoshida, K., & Kanaya, H. (2013). A design technique for a high-speed SAR ADC using non-binary search algorithm and redundancy. In 2013 Asia-Pacific Microwave Conference Proceedings, APMC 2013 (pp. 506-508). [6694846] (Asia-Pacific Microwave Conference Proceedings, APMC). https://doi.org/10.1109/APMC.2013.6694846