A Hardware Maze Router with Application to Interactive Rip-Up and Reroute

Kei Suzuki; Yusuke Matsunaga; Masayoshi Tachibana; Tatsuo Ohtsuki

doi:10.1109/TCAD.1986.1270218

A Hardware Maze Router with Application to Interactive Rip-Up and Reroute

Kei Suzuki, Yusuke Matsunaga, Masayoshi Tachibana, Tatsuo Ohtsuki

Research output: Contribution to journal › Article › peer-review

14 Citations (Scopus)

Abstract

This paper presents a new parallel-processing architecture for hardware routers based on the Lee algorithm. Unlike the existing machines, which require N2 processors to implement the Lee algorithm on an N x N grid plane, the proposed architecture requires only O(N) processors to find a path in O(N) time. A prototype machine with 64 processors has been developed to deal with a 128 × 128 grid plane. The architecture of the machine is discussed, together with its experimental performance data. Further, it is reported that the parallel-processed Lee algorithm is most useful and powerful when applied to interactive rip-up and reroute.

Original language	English
Pages (from-to)	466-476
Number of pages	11
Journal	IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume	5
Issue number	4
DOIs	https://doi.org/10.1109/TCAD.1986.1270218
Publication status	Published - Oct 1986
Externally published	Yes

All Science Journal Classification (ASJC) codes

Software
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

Access to Document

10.1109/TCAD.1986.1270218

Cite this

@article{0f25765b5b324e6d82b2bbd2fd520eef,

title = "A Hardware Maze Router with Application to Interactive Rip-Up and Reroute",

abstract = "This paper presents a new parallel-processing architecture for hardware routers based on the Lee algorithm. Unlike the existing machines, which require N2 processors to implement the Lee algorithm on an N x N grid plane, the proposed architecture requires only O(N) processors to find a path in O(N) time. A prototype machine with 64 processors has been developed to deal with a 128 × 128 grid plane. The architecture of the machine is discussed, together with its experimental performance data. Further, it is reported that the parallel-processed Lee algorithm is most useful and powerful when applied to interactive rip-up and reroute.",

author = "Kei Suzuki and Yusuke Matsunaga and Masayoshi Tachibana and Tatsuo Ohtsuki",

year = "1986",

month = oct,

doi = "10.1109/TCAD.1986.1270218",

language = "English",

volume = "5",

pages = "466--476",

journal = "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems",

issn = "0278-0070",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "4",

}

TY - JOUR

T1 - A Hardware Maze Router with Application to Interactive Rip-Up and Reroute

AU - Suzuki, Kei

AU - Matsunaga, Yusuke

AU - Tachibana, Masayoshi

AU - Ohtsuki, Tatsuo

PY - 1986/10

Y1 - 1986/10

N2 - This paper presents a new parallel-processing architecture for hardware routers based on the Lee algorithm. Unlike the existing machines, which require N2 processors to implement the Lee algorithm on an N x N grid plane, the proposed architecture requires only O(N) processors to find a path in O(N) time. A prototype machine with 64 processors has been developed to deal with a 128 × 128 grid plane. The architecture of the machine is discussed, together with its experimental performance data. Further, it is reported that the parallel-processed Lee algorithm is most useful and powerful when applied to interactive rip-up and reroute.

AB - This paper presents a new parallel-processing architecture for hardware routers based on the Lee algorithm. Unlike the existing machines, which require N2 processors to implement the Lee algorithm on an N x N grid plane, the proposed architecture requires only O(N) processors to find a path in O(N) time. A prototype machine with 64 processors has been developed to deal with a 128 × 128 grid plane. The architecture of the machine is discussed, together with its experimental performance data. Further, it is reported that the parallel-processed Lee algorithm is most useful and powerful when applied to interactive rip-up and reroute.

UR - http://www.scopus.com/inward/record.url?scp=84934027087&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84934027087&partnerID=8YFLogxK

U2 - 10.1109/TCAD.1986.1270218

DO - 10.1109/TCAD.1986.1270218

M3 - Article

AN - SCOPUS:84934027087

SN - 0278-0070

VL - 5

SP - 466

EP - 476

JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

IS - 4

ER -

A Hardware Maze Router with Application to Interactive Rip-Up and Reroute

Abstract

All Science Journal Classification (ASJC) codes

Access to Document

Other files and links

Fingerprint

Cite this