A high-efficiency good linearity 21 to 26.5 GHz fully integrated power amplifier using 0.18 μm CMOS technology

H. Mosalam, A. Allam, Adel Abdel-Rahman, T. Kaho, H. Jia, Ramesh K. Pokharel

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

This paper presents the design and implementation of a 21- 26.5 GHz broadband, two stages CMOS power amplifier (PA) for quasi-millimeter wave band wireless communication systems. The proposed PA is designed using staggered tuning method [1], which is employed for the first time in quasi-millimeter wave band. Moreover, source and load-pull simulation, in addition to, impedance analysis are employed to optimize the input, output, and inter-stage impedance matching circuits for maximum power added efficiency (PAE) and better linearity. The measurement results on a chip fabricated using 0.18 μm CMOS technology shows a power gain of 10.2 ± 0.8 dB, a maximum PAE and output gain compression point (POut1dB ) of 10.5 dBm and 18 %, respectively, at 24 GHz while consuming 42 mW only. In addition, the PA achieved excellent low measured group delay variations of 75 ± 22 ps.

Original languageEnglish
Title of host publication2016 IEEE 59th International Midwest Symposium on Circuits and Systems, MWSCAS 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509009169
DOIs
Publication statusPublished - Jul 2 2016
Event59th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2016 - Abu Dhabi, United Arab Emirates
Duration: Oct 16 2016Oct 19 2016

Publication series

NameMidwest Symposium on Circuits and Systems
Volume0
ISSN (Print)1548-3746

Other

Other59th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2016
Country/TerritoryUnited Arab Emirates
CityAbu Dhabi
Period10/16/1610/19/16

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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