Abstract
This paper proposes an on-chip memory-path architecture employing the dynamically variable line-size (D-VLS) cache for high performance and low energy consumption. The D-VLS cache exploits the high on-chip memory bandwidth attainable on merged DRAM/logic LSIs by replacing a whole large cache line in one cycle. At the same time, it attempts to avoid frequent evictions by decreasing the cache-line size when programs have poor spatial locality. Activating only on-chip DRAM subarrays corresponding to a replaced cache-line size produces a significant energy reduction. In our simulation, it is observed that our proposed on-chip memory-path architecture, which employs a direct-mapped D-VLS cache, improves the ED (Energy Delay) product by more than 75% over a conventional memory-path model.
| Original language | English |
|---|---|
| Pages (from-to) | 1716-1722 |
| Number of pages | 7 |
| Journal | IEICE Transactions on Electronics |
| Volume | E83-C |
| Issue number | 11 |
| Publication status | Published - 2000 |
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All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
Cite this
A high-performance/low-power on-chip memory-path architecture with variable cache-line size. / Koji, Inoue; Kai, Koji; Murakami, Kazuaki.
In: IEICE Transactions on Electronics, Vol. E83-C, No. 11, 2000, p. 1716-1722.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - A high-performance/low-power on-chip memory-path architecture with variable cache-line size
AU - Koji, Inoue
AU - Kai, Koji
AU - Murakami, Kazuaki
PY - 2000
Y1 - 2000
N2 - This paper proposes an on-chip memory-path architecture employing the dynamically variable line-size (D-VLS) cache for high performance and low energy consumption. The D-VLS cache exploits the high on-chip memory bandwidth attainable on merged DRAM/logic LSIs by replacing a whole large cache line in one cycle. At the same time, it attempts to avoid frequent evictions by decreasing the cache-line size when programs have poor spatial locality. Activating only on-chip DRAM subarrays corresponding to a replaced cache-line size produces a significant energy reduction. In our simulation, it is observed that our proposed on-chip memory-path architecture, which employs a direct-mapped D-VLS cache, improves the ED (Energy Delay) product by more than 75% over a conventional memory-path model.
AB - This paper proposes an on-chip memory-path architecture employing the dynamically variable line-size (D-VLS) cache for high performance and low energy consumption. The D-VLS cache exploits the high on-chip memory bandwidth attainable on merged DRAM/logic LSIs by replacing a whole large cache line in one cycle. At the same time, it attempts to avoid frequent evictions by decreasing the cache-line size when programs have poor spatial locality. Activating only on-chip DRAM subarrays corresponding to a replaced cache-line size produces a significant energy reduction. In our simulation, it is observed that our proposed on-chip memory-path architecture, which employs a direct-mapped D-VLS cache, improves the ED (Energy Delay) product by more than 75% over a conventional memory-path model.
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M3 - Article
AN - SCOPUS:33746341818
VL - E83-C
SP - 1716
EP - 1722
JO - IEICE Transactions on Electronics
JF - IEICE Transactions on Electronics
SN - 0916-8524
IS - 11
ER -