A high-performance/low-power on-chip memory-path architecture with variable cache-line size

Inoue Koji, Koji Kai, Kazuaki Murakami

Research output: Contribution to journalArticlepeer-review

5 Citations (Scopus)

Abstract

This paper proposes an on-chip memory-path architecture employing the dynamically variable line-size (D-VLS) cache for high performance and low energy consumption. The D-VLS cache exploits the high on-chip memory bandwidth attainable on merged DRAM/logic LSIs by replacing a whole large cache line in one cycle. At the same time, it attempts to avoid frequent evictions by decreasing the cache-line size when programs have poor spatial locality. Activating only on-chip DRAM subarrays corresponding to a replaced cache-line size produces a significant energy reduction. In our simulation, it is observed that our proposed on-chip memory-path architecture, which employs a direct-mapped D-VLS cache, improves the ED (Energy Delay) product by more than 75% over a conventional memory-path model.

Original languageEnglish
Pages (from-to)1716-1722
Number of pages7
JournalIEICE Transactions on Electronics
VolumeE83-C
Issue number11
Publication statusPublished - 2000

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Fingerprint

Dive into the research topics of 'A high-performance/low-power on-chip memory-path architecture with variable cache-line size'. Together they form a unique fingerprint.

Cite this