A low energy set-associative I-cache with extended BTB

Koji Inoue, Vasily G. Moshnyaga, Kazuaki Murakami

Research output: Contribution to journalArticlepeer-review

6 Citations (Scopus)

Abstract

This paper proposes a low-energy instruction-cache architecture, called history-based tag-comparison (HBTC) cache. The HBTC cache attempts to re-use tag-comparison results for avoiding unnecessary way activation in set-associative caches. The cache records tag-comparison results in an extended BTB, and re-uses them for directly selecting only the hit-way which includes the target instruction. In our simulation, it is observed that the HBTC cache can achieve 62% of energy reduction, with less than 1% performance degradation, compared with a conventional cache.

Original languageEnglish
Article number32
Pages (from-to)187-192
Number of pages6
JournalProceedings-IEEE International Conference on Computer Design: VLSI in Computers and Processors
DOIs
Publication statusPublished - Jan 1 2002
Externally publishedYes

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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