A low-glitch and small-logic-area Fibonacci Series DAC

Kazuya Hokazono; Daisuke Kanemoto; Ramesh Pokharel; Abhishek Tomar; Haruichi Kanaya; Keiji Yoshida

doi:10.1109/MWSCAS.2011.6026342

A low-glitch and small-logic-area Fibonacci Series DAC

Kazuya Hokazono, Daisuke Kanemoto, Ramesh Pokharel, Abhishek Tomar, Haruichi Kanaya, Keiji Yoshida

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

A novel Digital-to-Analog Converter (DAC) utilizing Fibonacci Series is presented in this paper. The ratios of successive weights are smaller than those of binary DAC and larger than those of unary DAC. The features of the proposed DAC are lower glitch-energy than a binary DAC and the number of logic gates is less than a unary DAC. In the proposed DAC in 0.18μm CMOS process, the glitch-energy of the proposed DAC can be reduced by 75% compared to that of binary DAC, and the number of logic gates can be achieved an around 42% reduction compared to that of the unary DAC. We fabricated a prototype 6-bit Fibonacci Series DAC in order to confirm the operation.

Original language	English
Title of host publication	54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011
DOIs	https://doi.org/10.1109/MWSCAS.2011.6026342
Publication status	Published - Oct 13 2011
Event	54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011 - Seoul, Korea, Republic of Duration: Aug 7 2011 → Aug 10 2011

Publication series

Name	Midwest Symposium on Circuits and Systems
ISSN (Print)	1548-3746

Other

Other	54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011
Country/Territory	Korea, Republic of
City	Seoul
Period	8/7/11 → 8/10/11

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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10.1109/MWSCAS.2011.6026342

Cite this

Hokazono, K, Kanemoto, D, Pokharel, R, Tomar, A, Kanaya, H & Yoshida, K 2011, A low-glitch and small-logic-area Fibonacci Series DAC. in 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011., 6026342, Midwest Symposium on Circuits and Systems, 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011, Seoul, Korea, Republic of, 8/7/11. https://doi.org/10.1109/MWSCAS.2011.6026342

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abstract = "A novel Digital-to-Analog Converter (DAC) utilizing Fibonacci Series is presented in this paper. The ratios of successive weights are smaller than those of binary DAC and larger than those of unary DAC. The features of the proposed DAC are lower glitch-energy than a binary DAC and the number of logic gates is less than a unary DAC. In the proposed DAC in 0.18μm CMOS process, the glitch-energy of the proposed DAC can be reduced by 75% compared to that of binary DAC, and the number of logic gates can be achieved an around 42% reduction compared to that of the unary DAC. We fabricated a prototype 6-bit Fibonacci Series DAC in order to confirm the operation.",

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AU - Hokazono, Kazuya

AU - Kanemoto, Daisuke

AU - Pokharel, Ramesh

AU - Tomar, Abhishek

AU - Kanaya, Haruichi

AU - Yoshida, Keiji

PY - 2011/10/13

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N2 - A novel Digital-to-Analog Converter (DAC) utilizing Fibonacci Series is presented in this paper. The ratios of successive weights are smaller than those of binary DAC and larger than those of unary DAC. The features of the proposed DAC are lower glitch-energy than a binary DAC and the number of logic gates is less than a unary DAC. In the proposed DAC in 0.18μm CMOS process, the glitch-energy of the proposed DAC can be reduced by 75% compared to that of binary DAC, and the number of logic gates can be achieved an around 42% reduction compared to that of the unary DAC. We fabricated a prototype 6-bit Fibonacci Series DAC in order to confirm the operation.

AB - A novel Digital-to-Analog Converter (DAC) utilizing Fibonacci Series is presented in this paper. The ratios of successive weights are smaller than those of binary DAC and larger than those of unary DAC. The features of the proposed DAC are lower glitch-energy than a binary DAC and the number of logic gates is less than a unary DAC. In the proposed DAC in 0.18μm CMOS process, the glitch-energy of the proposed DAC can be reduced by 75% compared to that of binary DAC, and the number of logic gates can be achieved an around 42% reduction compared to that of the unary DAC. We fabricated a prototype 6-bit Fibonacci Series DAC in order to confirm the operation.

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A low-glitch and small-logic-area Fibonacci Series DAC

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