A low-glitch and small-logic-area Fibonacci Series DAC

Kazuya Hokazono, Daisuke Kanemoto, Ramesh Pokharel, Abhishek Tomar, Haruichi Kanaya, Keiji Yoshida

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

A novel Digital-to-Analog Converter (DAC) utilizing Fibonacci Series is presented in this paper. The ratios of successive weights are smaller than those of binary DAC and larger than those of unary DAC. The features of the proposed DAC are lower glitch-energy than a binary DAC and the number of logic gates is less than a unary DAC. In the proposed DAC in 0.18μm CMOS process, the glitch-energy of the proposed DAC can be reduced by 75% compared to that of binary DAC, and the number of logic gates can be achieved an around 42% reduction compared to that of the unary DAC. We fabricated a prototype 6-bit Fibonacci Series DAC in order to confirm the operation.

Original languageEnglish
Title of host publication54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011
DOIs
Publication statusPublished - Oct 13 2011
Event54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011 - Seoul, Korea, Republic of
Duration: Aug 7 2011Aug 10 2011

Publication series

NameMidwest Symposium on Circuits and Systems
ISSN (Print)1548-3746

Other

Other54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011
CountryKorea, Republic of
CitySeoul
Period8/7/118/10/11

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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