A low-power and GHz-Band LC-DCO directly drives 10mm on-chip clock distribution line in 0.18 μm CMOS

Masahiro Ichihashi, Haruichi Kanaya

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

High-speed clock distribution design is becoming increasingly difficult and challenging task due to the huge power consumption and jitter caused by large capacitive loading and multiple repeater stages. This paper proposes a novel low-power, GHz-band bufferless LC-DCO which directly drives 10 mm on-chip clock distribution line for high-speed serial links. The shared LC-tank structure between DCO frequency tuning capacitor and clock distribution line mitigate the frequency sensitivity and makes an energy-efficient, area-saving, high-speed operation possible. The test-chip is implemented under TSMC 0.18 μm, 1-poly, 6-metal CMOS technology and the core area of proposed LC-DCO is only 270 × 280 μm2. The full-chip post layout simulation results show 2.54 GHz oscillation frequency, 2.2mA current consumption and phase noise of -123 dBc/Hz at 1MHz offset.

Original languageEnglish
Pages (from-to)1907-1914
Number of pages8
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE101A
Issue number11
DOIs
Publication statusPublished - Nov 1 2018

Fingerprint

Clocks
High Speed
Chip
Line
Phase Noise
Telecommunication repeaters
Jitter
Phase noise
Capacitor
Energy Efficient
Power Consumption
Layout
Tuning
Electric power utilization
Capacitors
Metals
Oscillation
Simulation
Design
Mm

All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering
  • Applied Mathematics

Cite this

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