TY - JOUR
T1 - A low-power and GHz-Band LC-DCO directly drives 10mm on-chip clock distribution line in 0.18 μm CMOS
AU - Ichihashi, Masahiro
AU - Kanaya, Haruichi
N1 - Funding Information:
This work was partly supported by KAKENHI (JP18K04146) from Japan Science and Technology Agency, JST and also partly supported by VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with Keysight Technologies.
Publisher Copyright:
© 2018 The Institute of Electronics, Information and Communication Engineers.
PY - 2018/11
Y1 - 2018/11
N2 - High-speed clock distribution design is becoming increasingly difficult and challenging task due to the huge power consumption and jitter caused by large capacitive loading and multiple repeater stages. This paper proposes a novel low-power, GHz-band bufferless LC-DCO which directly drives 10 mm on-chip clock distribution line for high-speed serial links. The shared LC-tank structure between DCO frequency tuning capacitor and clock distribution line mitigate the frequency sensitivity and makes an energy-efficient, area-saving, high-speed operation possible. The test-chip is implemented under TSMC 0.18 μm, 1-poly, 6-metal CMOS technology and the core area of proposed LC-DCO is only 270 × 280 μm2. The full-chip post layout simulation results show 2.54 GHz oscillation frequency, 2.2mA current consumption and phase noise of -123 dBc/Hz at 1MHz offset.
AB - High-speed clock distribution design is becoming increasingly difficult and challenging task due to the huge power consumption and jitter caused by large capacitive loading and multiple repeater stages. This paper proposes a novel low-power, GHz-band bufferless LC-DCO which directly drives 10 mm on-chip clock distribution line for high-speed serial links. The shared LC-tank structure between DCO frequency tuning capacitor and clock distribution line mitigate the frequency sensitivity and makes an energy-efficient, area-saving, high-speed operation possible. The test-chip is implemented under TSMC 0.18 μm, 1-poly, 6-metal CMOS technology and the core area of proposed LC-DCO is only 270 × 280 μm2. The full-chip post layout simulation results show 2.54 GHz oscillation frequency, 2.2mA current consumption and phase noise of -123 dBc/Hz at 1MHz offset.
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U2 - 10.1587/transfun.E101.A.1907
DO - 10.1587/transfun.E101.A.1907
M3 - Article
AN - SCOPUS:85056077631
VL - E101A
SP - 1907
EP - 1914
JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
SN - 0916-8508
IS - 11
ER -