A low-power digital matched filter for spread-spectrum systems

Shoji Goto; Takashi Yamada; Norihisa Takayama; Yoshifumi Matsushita; Yasoo Harada; Hiroto Yasuura

doi:10.1109/lpe.2002.146759

A low-power digital matched filter for spread-spectrum systems

Shoji Goto, Takashi Yamada, Norihisa Takayama, Yoshifumi Matsushita, Yasoo Harada, Hiroto Yasuura

Research output: Contribution to conference › Paper › peer-review

6 Citations (Scopus)

Abstract

A Digital Matched Filter (DMF) is an essential device for Direct-Sequence Spread-Spectrum (DS-SS) communication systems. Reducing the power consumption of a DMF is especially critical for battery-powered terminals. The reception registers and the correlation-calculating unit dissipate the majority of the power in a DMF. In this paper we discuss this problem and propose a low-power architectural approach to a DMF. The total switching activity factor and the switched capacitance are reduced. As a result of power analysis at the gate level, the implementation of the proposed architecture in a standard 0.18-μm CMOS technology achieved a reduction in the power consumption of more than 70%.

Original language	English
Pages	301-306
Number of pages	6
DOIs	https://doi.org/10.1109/lpe.2002.146759
Publication status	Published - 2002
Externally published	Yes
Event	Proceedings of the 2002 International Symposium on Low Power Electronics and Design - Monterey, CA, United States Duration: Aug 12 2002 → Aug 14 2002

Other

Other	Proceedings of the 2002 International Symposium on Low Power Electronics and Design
Country/Territory	United States
City	Monterey, CA
Period	8/12/02 → 8/14/02

All Science Journal Classification (ASJC) codes

Engineering(all)

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10.1109/lpe.2002.146759

Cite this

A low-power digital matched filter for spread-spectrum systems. / Goto, Shoji; Yamada, Takashi; Takayama, Norihisa; Matsushita, Yoshifumi; Harada, Yasoo; Yasuura, Hiroto.

2002. 301-306 Paper presented at Proceedings of the 2002 International Symposium on Low Power Electronics and Design, Monterey, CA, United States.

Research output: Contribution to conference › Paper › peer-review

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abstract = "A Digital Matched Filter (DMF) is an essential device for Direct-Sequence Spread-Spectrum (DS-SS) communication systems. Reducing the power consumption of a DMF is especially critical for battery-powered terminals. The reception registers and the correlation-calculating unit dissipate the majority of the power in a DMF. In this paper we discuss this problem and propose a low-power architectural approach to a DMF. The total switching activity factor and the switched capacitance are reduced. As a result of power analysis at the gate level, the implementation of the proposed architecture in a standard 0.18-μm CMOS technology achieved a reduction in the power consumption of more than 70%.",

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doi = "10.1109/lpe.2002.146759",

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AU - Goto, Shoji

AU - Yamada, Takashi

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AU - Harada, Yasoo

AU - Yasuura, Hiroto

PY - 2002

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N2 - A Digital Matched Filter (DMF) is an essential device for Direct-Sequence Spread-Spectrum (DS-SS) communication systems. Reducing the power consumption of a DMF is especially critical for battery-powered terminals. The reception registers and the correlation-calculating unit dissipate the majority of the power in a DMF. In this paper we discuss this problem and propose a low-power architectural approach to a DMF. The total switching activity factor and the switched capacitance are reduced. As a result of power analysis at the gate level, the implementation of the proposed architecture in a standard 0.18-μm CMOS technology achieved a reduction in the power consumption of more than 70%.

AB - A Digital Matched Filter (DMF) is an essential device for Direct-Sequence Spread-Spectrum (DS-SS) communication systems. Reducing the power consumption of a DMF is especially critical for battery-powered terminals. The reception registers and the correlation-calculating unit dissipate the majority of the power in a DMF. In this paper we discuss this problem and propose a low-power architectural approach to a DMF. The total switching activity factor and the switched capacitance are reduced. As a result of power analysis at the gate level, the implementation of the proposed architecture in a standard 0.18-μm CMOS technology achieved a reduction in the power consumption of more than 70%.

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Y2 - 12 August 2002 through 14 August 2002

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A low-power digital matched filter for spread-spectrum systems

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