Abstract
A Digital Matched Filter (DMF) is an essential device for Direct-Sequence Spread-Spectrum (DS-SS) communication systems. Reducing the power consumption of a DMF is especially critical for battery-powered terminals. The reception registers and the correlation-calculating unit dissipate the majority of the power in a DMF. In this paper we discuss this problem and propose a low-power architectural approach to a DMF. The total switching activity factor and the switched capacitance are reduced. As a result of power analysis at the gate level, the implementation of the proposed architecture in a standard 0.18-μm CMOS technology achieved a reduction in the power consumption of more than 70%.
Original language | English |
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Pages | 301-306 |
Number of pages | 6 |
DOIs | |
Publication status | Published - 2002 |
Externally published | Yes |
Event | Proceedings of the 2002 International Symposium on Low Power Electronics and Design - Monterey, CA, United States Duration: Aug 12 2002 → Aug 14 2002 |
Other
Other | Proceedings of the 2002 International Symposium on Low Power Electronics and Design |
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Country/Territory | United States |
City | Monterey, CA |
Period | 8/12/02 → 8/14/02 |
All Science Journal Classification (ASJC) codes
- Engineering(all)