A low-power I-cache design with tag-comparison reuse

Koji Inoue, Hidekazu Tanaka, Vasily G. Moshnyaga, Kazuaki Murakami

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)


This paper reports design and evaluation results of a low-energy I-cache architecture, called history-based tag-comparison (HBTC) cache. The HBTC cache attempts to re-use tag-comparison results to detect and eliminate unnecessary memory-array activations. We have performed cycle accurate simulations, and have designed an SRAM core based on a 0.18 μm CMOS technology. As a result, it has been observed that the HBTC approach can achieve 60% of energy reduction, with only 0.3% performance degradation, compared to a conventional cache. Furthermore, we have also evaluated the potential of the HBTC cache by combining with other low-energy techniques.

Original languageEnglish
Title of host publication2004 International Symposium on System-on-Chip Proceedings
EditorsJ. Nurmi, J. Takala, T.D. Hamalainen
Number of pages7
Publication statusPublished - 2004
Externally publishedYes
Event2004 International Symposium on System-on-Chip - Tampere, Finland
Duration: Nov 16 2004Nov 18 2004

Publication series

Name2004 International Symposium on System-on-Chip Proceedings


Other2004 International Symposium on System-on-Chip

All Science Journal Classification (ASJC) codes

  • Engineering(all)


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