A low-power I-cache design with tag-comparison reuse

Koji Inoue; Hidekazu Tanaka; Vasily G. Moshnyaga; Kazuaki Murakami

A low-power I-cache design with tag-comparison reuse

Koji Inoue, Hidekazu Tanaka, Vasily G. Moshnyaga, Kazuaki Murakami

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper reports design and evaluation results of a low-energy I-cache architecture, called history-based tag-comparison (HBTC) cache. The HBTC cache attempts to re-use tag-comparison results to detect and eliminate unnecessary memory-array activations. We have performed cycle accurate simulations, and have designed an SRAM core based on a 0.18 μm CMOS technology. As a result, it has been observed that the HBTC approach can achieve 60% of energy reduction, with only 0.3% performance degradation, compared to a conventional cache. Furthermore, we have also evaluated the potential of the HBTC cache by combining with other low-energy techniques.

Original language	English
Title of host publication	2004 International Symposium on System-on-Chip Proceedings
Editors	J. Nurmi, J. Takala, T.D. Hamalainen
Pages	61-67
Number of pages	7
Publication status	Published - 2004
Externally published	Yes
Event	2004 International Symposium on System-on-Chip - Tampere, Finland Duration: Nov 16 2004 → Nov 18 2004

Publication series

Name	2004 International Symposium on System-on-Chip Proceedings

Other

Other	2004 International Symposium on System-on-Chip
Country/Territory	Finland
City	Tampere
Period	11/16/04 → 11/18/04

All Science Journal Classification (ASJC) codes

Engineering(all)

Cite this

A low-power I-cache design with tag-comparison reuse. / Inoue, Koji; Tanaka, Hidekazu; Moshnyaga, Vasily G.; Murakami, Kazuaki.

2004 International Symposium on System-on-Chip Proceedings. ed. / J. Nurmi; J. Takala; T.D. Hamalainen. 2004. p. 61-67 (2004 International Symposium on System-on-Chip Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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title = "A low-power I-cache design with tag-comparison reuse",

abstract = "This paper reports design and evaluation results of a low-energy I-cache architecture, called history-based tag-comparison (HBTC) cache. The HBTC cache attempts to re-use tag-comparison results to detect and eliminate unnecessary memory-array activations. We have performed cycle accurate simulations, and have designed an SRAM core based on a 0.18 μm CMOS technology. As a result, it has been observed that the HBTC approach can achieve 60% of energy reduction, with only 0.3% performance degradation, compared to a conventional cache. Furthermore, we have also evaluated the potential of the HBTC cache by combining with other low-energy techniques.",

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N2 - This paper reports design and evaluation results of a low-energy I-cache architecture, called history-based tag-comparison (HBTC) cache. The HBTC cache attempts to re-use tag-comparison results to detect and eliminate unnecessary memory-array activations. We have performed cycle accurate simulations, and have designed an SRAM core based on a 0.18 μm CMOS technology. As a result, it has been observed that the HBTC approach can achieve 60% of energy reduction, with only 0.3% performance degradation, compared to a conventional cache. Furthermore, we have also evaluated the potential of the HBTC cache by combining with other low-energy techniques.

AB - This paper reports design and evaluation results of a low-energy I-cache architecture, called history-based tag-comparison (HBTC) cache. The HBTC cache attempts to re-use tag-comparison results to detect and eliminate unnecessary memory-array activations. We have performed cycle accurate simulations, and have designed an SRAM core based on a 0.18 μm CMOS technology. As a result, it has been observed that the HBTC approach can achieve 60% of energy reduction, with only 0.3% performance degradation, compared to a conventional cache. Furthermore, we have also evaluated the potential of the HBTC cache by combining with other low-energy techniques.

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M3 - Conference contribution

AN - SCOPUS:21244455228

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T3 - 2004 International Symposium on System-on-Chip Proceedings

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BT - 2004 International Symposium on System-on-Chip Proceedings

A2 - Nurmi, J.

A2 - Takala, J.

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T2 - 2004 International Symposium on System-on-Chip

Y2 - 16 November 2004 through 18 November 2004

ER -

A low-power I-cache design with tag-comparison reuse

Abstract

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All Science Journal Classification (ASJC) codes

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