TY - GEN
T1 - A low-power I-cache design with tag-comparison reuse
AU - Inoue, Koji
AU - Tanaka, Hidekazu
AU - Moshnyaga, Vasily G.
AU - Murakami, Kazuaki
N1 - Copyright:
Copyright 2008 Elsevier B.V., All rights reserved.
PY - 2004
Y1 - 2004
N2 - This paper reports design and evaluation results of a low-energy I-cache architecture, called history-based tag-comparison (HBTC) cache. The HBTC cache attempts to re-use tag-comparison results to detect and eliminate unnecessary memory-array activations. We have performed cycle accurate simulations, and have designed an SRAM core based on a 0.18 μm CMOS technology. As a result, it has been observed that the HBTC approach can achieve 60% of energy reduction, with only 0.3% performance degradation, compared to a conventional cache. Furthermore, we have also evaluated the potential of the HBTC cache by combining with other low-energy techniques.
AB - This paper reports design and evaluation results of a low-energy I-cache architecture, called history-based tag-comparison (HBTC) cache. The HBTC cache attempts to re-use tag-comparison results to detect and eliminate unnecessary memory-array activations. We have performed cycle accurate simulations, and have designed an SRAM core based on a 0.18 μm CMOS technology. As a result, it has been observed that the HBTC approach can achieve 60% of energy reduction, with only 0.3% performance degradation, compared to a conventional cache. Furthermore, we have also evaluated the potential of the HBTC cache by combining with other low-energy techniques.
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M3 - Conference contribution
AN - SCOPUS:21244455228
SN - 0780385586
T3 - 2004 International Symposium on System-on-Chip Proceedings
SP - 61
EP - 67
BT - 2004 International Symposium on System-on-Chip Proceedings
A2 - Nurmi, J.
A2 - Takala, J.
A2 - Hamalainen, T.D.
T2 - 2004 International Symposium on System-on-Chip
Y2 - 16 November 2004 through 18 November 2004
ER -