A low-power implementation of arctangent function for communication applications using FPGA

M. Saber, Yutaka Jitsumatsu, T. Kohda

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

Abstract

A low power architecture to compute arctangent function which is suitable for broad-band communication applications is presented. This architecture aims to avoid high power consumption and long latency which are the main disadvantages to other methods based on CORDIC algorithm or conventional LUT methods or polynomial approximation. The architecture is implemented using FPGA, computes arctangent function with 3 clock pulses, and it is power dissipation is lower than Cordic algorithm by 80%.

Original languageEnglish
Title of host publicationProceedings of the 4th International Workshop on Signal Design and Its Applications in Communications, IWSDA'09
Pages60-63
Number of pages4
DOIs
Publication statusPublished - Dec 1 2009
Event4th International Workshop on Signal Design and Its Applications in Communications, IWSDA'09 - Fukuoka, Japan
Duration: Oct 19 2009Oct 23 2009

Publication series

NameProceedings of the 4th International Workshop on Signal Design and Its Applications in Communications, IWSDA'09

Other

Other4th International Workshop on Signal Design and Its Applications in Communications, IWSDA'09
CountryJapan
CityFukuoka
Period10/19/0910/23/09

All Science Journal Classification (ASJC) codes

  • Computer Networks and Communications
  • Signal Processing
  • Electrical and Electronic Engineering
  • Communication

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    Saber, M., Jitsumatsu, Y., & Kohda, T. (2009). A low-power implementation of arctangent function for communication applications using FPGA. In Proceedings of the 4th International Workshop on Signal Design and Its Applications in Communications, IWSDA'09 (pp. 60-63). [5346438] (Proceedings of the 4th International Workshop on Signal Design and Its Applications in Communications, IWSDA'09). https://doi.org/10.1109/IWSDA.2009.5346438