A low-temperature fabricated gate-stack structure for Ge-based MOSFET with ferromagnetic epitaxial Heusler-alloy/Ge electrodes

Yuichi Fujita, Michihiro Yamada, Yuta Nagatomi, Keisuke Yamamoto, Shinya Yamada, Kentarou Sawano, Takeshi Kanashima, Hiroshi Nakashima, Kohei Hamaya

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

A possible low-temperature fabrication process of a gate-stack for Ge-based spin metal-oxide-semiconductor field-effect transistor (MOSFET) is investigated. First, since we use epitaxial ferromagnetic Heusler alloys on top of the phosphorous doped Ge epilayer as spin injector and detector, we need a dry etching process to form Heusler-alloy/n+-Ge Schottky-tunnel contacts. Next, to remove the Ge epilayers damaged by the dry etching process, the fabricated structures are dipped in a 0.03% diluted H2O2 solution. Finally, Al/SiO2/GeO2/Ge gate-stack structures are fabricated at 300 °C as a top gate-stack structure. As a result, the currents in the Ge-MOSFET fabricated here can be modulated by applying gate voltages even by using the low-temperature formed gate-stack structures. This low-temperature fabrication process can be utilized for operating Ge spin MOSFETs with a top gate electrode.

Original languageEnglish
Article number63001
JournalJapanese Journal of Applied Physics
Volume55
Issue number6
DOIs
Publication statusPublished - Jun 2016

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MOSFET devices
metal oxide semiconductors
Dry etching
field effect transistors
Epilayers
Electrodes
electrodes
Fabrication
Temperature
Tunnels
etching
Detectors
fabrication
Electric potential
injectors
tunnels
detectors
electric potential

All Science Journal Classification (ASJC) codes

  • Engineering(all)
  • Physics and Astronomy(all)

Cite this

A low-temperature fabricated gate-stack structure for Ge-based MOSFET with ferromagnetic epitaxial Heusler-alloy/Ge electrodes. / Fujita, Yuichi; Yamada, Michihiro; Nagatomi, Yuta; Yamamoto, Keisuke; Yamada, Shinya; Sawano, Kentarou; Kanashima, Takeshi; Nakashima, Hiroshi; Hamaya, Kohei.

In: Japanese Journal of Applied Physics, Vol. 55, No. 6, 63001, 06.2016.

Research output: Contribution to journalArticle

Fujita, Yuichi ; Yamada, Michihiro ; Nagatomi, Yuta ; Yamamoto, Keisuke ; Yamada, Shinya ; Sawano, Kentarou ; Kanashima, Takeshi ; Nakashima, Hiroshi ; Hamaya, Kohei. / A low-temperature fabricated gate-stack structure for Ge-based MOSFET with ferromagnetic epitaxial Heusler-alloy/Ge electrodes. In: Japanese Journal of Applied Physics. 2016 ; Vol. 55, No. 6.
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AU - Yamamoto, Keisuke

AU - Yamada, Shinya

AU - Sawano, Kentarou

AU - Kanashima, Takeshi

AU - Nakashima, Hiroshi

AU - Hamaya, Kohei

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