A micro-vectorprocessor Architecture - Performance Modeling and Benchmarking -

Takashi Hashimoto, Tetsuo Hironaka, Kazuaki Murakami, Hiroto Yasuura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper proposes and examines some architectural features suitable for micro-vectorprocessors. Due to the I/O-pin bottleneck, micro-vectorprocessors should save the off-chip memory bandwidth by exploiting the on-chip register bandwidth instead. Those features include the vector-instruction-level multithreading and FIFO vector registers. There are three variations of multithreading: periodic, forced, and round-robin. The paper also formulates the performance of micro-vectorprocessors with such architectural features. And then, the paper evaluates the performance attainable by those micro-vectorprocessors through software simulation. From the benchmark results, it is found that the vector-instruction-level multithreading and FIFO vector registers can improve the performance of the micro-vectorprocessors with the half memory bandwidth comparable to that of ones with the full memory bandwidth. Furthermore, forced multithreading is found to be tolerant to the large memory access latency. From these results, the paper concludes that the forced multithreading at the vector-instruction level is a good candidate for the architectural features suitable to micro-vectorprocessors.

Original languageEnglish
Title of host publicationProceedings of the 7th International Conference on Supercomputing, ICS 1993
PublisherAssociation for Computing Machinery
Pages308-317
Number of pages10
ISBN (Electronic)089791600X
DOIs
Publication statusPublished - Aug 1 1993
Event7th International Conference on Supercomputing, ICS 1993 - Tokyo, Japan
Duration: Jul 19 1993Jul 23 1993

Publication series

NameProceedings of the International Conference on Supercomputing
VolumePart F129670

Other

Other7th International Conference on Supercomputing, ICS 1993
CountryJapan
CityTokyo
Period7/19/937/23/93

Fingerprint

Benchmarking
Bandwidth
Data storage equipment

All Science Journal Classification (ASJC) codes

  • Computer Science(all)

Cite this

Hashimoto, T., Hironaka, T., Murakami, K., & Yasuura, H. (1993). A micro-vectorprocessor Architecture - Performance Modeling and Benchmarking -. In Proceedings of the 7th International Conference on Supercomputing, ICS 1993 (pp. 308-317). (Proceedings of the International Conference on Supercomputing; Vol. Part F129670). Association for Computing Machinery. https://doi.org/10.1145/165939.166000

A micro-vectorprocessor Architecture - Performance Modeling and Benchmarking -. / Hashimoto, Takashi; Hironaka, Tetsuo; Murakami, Kazuaki; Yasuura, Hiroto.

Proceedings of the 7th International Conference on Supercomputing, ICS 1993. Association for Computing Machinery, 1993. p. 308-317 (Proceedings of the International Conference on Supercomputing; Vol. Part F129670).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hashimoto, T, Hironaka, T, Murakami, K & Yasuura, H 1993, A micro-vectorprocessor Architecture - Performance Modeling and Benchmarking -. in Proceedings of the 7th International Conference on Supercomputing, ICS 1993. Proceedings of the International Conference on Supercomputing, vol. Part F129670, Association for Computing Machinery, pp. 308-317, 7th International Conference on Supercomputing, ICS 1993, Tokyo, Japan, 7/19/93. https://doi.org/10.1145/165939.166000
Hashimoto T, Hironaka T, Murakami K, Yasuura H. A micro-vectorprocessor Architecture - Performance Modeling and Benchmarking -. In Proceedings of the 7th International Conference on Supercomputing, ICS 1993. Association for Computing Machinery. 1993. p. 308-317. (Proceedings of the International Conference on Supercomputing). https://doi.org/10.1145/165939.166000
Hashimoto, Takashi ; Hironaka, Tetsuo ; Murakami, Kazuaki ; Yasuura, Hiroto. / A micro-vectorprocessor Architecture - Performance Modeling and Benchmarking -. Proceedings of the 7th International Conference on Supercomputing, ICS 1993. Association for Computing Machinery, 1993. pp. 308-317 (Proceedings of the International Conference on Supercomputing).
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