TY - JOUR
T1 - A module generator of 2-level neuron MOS circuits
AU - Ike, K.
AU - Hirose, K.
AU - Yasuura, H.
N1 - Funding Information:
The authors would like to thank Tadahiro Ohmi, Tadashi Shibata and Koji Kotani of Tohoku University, and all other people of their laboratory for their useful advice and for providing their data of neuMOS. The authors are grateful to the members of Yasuura Laboratory of Kyushu University for their helpful discussions. This work was partially supported by the Ministry of Education, Science, Sports, and Culture under Grant-in-Aid for Scientific Research on Priority Areas, “Ultimate Integration of Intelligence on Silicon Electronic Systems” (Head Investigator: Tadahiro Ohmi, Tohoku University).
PY - 1998/1/1
Y1 - 1998/1/1
N2 - A neuron MOS transistor, abbreviated to a neuMOS, has more than two input gates. It is a highly functional device and has a potential to reduce the number of transistors and the area, compared with CMOS circuits. We propose a module generator which generates 2-level neuMOS circuits for logic functions with small numbers of input variables. Using the module generator, we show 2-level neuMOS circuits for all 3-variable logic functions.
AB - A neuron MOS transistor, abbreviated to a neuMOS, has more than two input gates. It is a highly functional device and has a potential to reduce the number of transistors and the area, compared with CMOS circuits. We propose a module generator which generates 2-level neuMOS circuits for logic functions with small numbers of input variables. Using the module generator, we show 2-level neuMOS circuits for all 3-variable logic functions.
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U2 - 10.1016/S0045-7906(97)00040-2
DO - 10.1016/S0045-7906(97)00040-2
M3 - Article
AN - SCOPUS:0004953522
VL - 24
SP - 33
EP - 41
JO - Computers and Electrical Engineering
JF - Computers and Electrical Engineering
SN - 0045-7906
IS - 1-2
ER -