Abstract
A neuron MOS transistor, abbreviated to a neuMOS, has more than two input gates. It is a highly functional device and has a potential to reduce the number of transistors and the area, compared with CMOS circuits. We propose a module generator which generates 2-level neuMOS circuits for logic functions with small numbers of input variables. Using the module generator, we show 2-level neuMOS circuits for all 3-variable logic functions.
| Original language | English |
|---|---|
| Pages (from-to) | 33-41 |
| Number of pages | 9 |
| Journal | Computers and Electrical Engineering |
| Volume | 24 |
| Issue number | 1-2 |
| DOIs | |
| Publication status | Published - Jan 1 1998 |
Fingerprint
All Science Journal Classification (ASJC) codes
- Control and Systems Engineering
- Computer Science(all)
- Electrical and Electronic Engineering
Cite this
A module generator of 2-level neuron MOS circuits. / Ike, K.; Hirose, K.; Yasuura, Hiroto.
In: Computers and Electrical Engineering, Vol. 24, No. 1-2, 01.01.1998, p. 33-41.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - A module generator of 2-level neuron MOS circuits
AU - Ike, K.
AU - Hirose, K.
AU - Yasuura, Hiroto
PY - 1998/1/1
Y1 - 1998/1/1
N2 - A neuron MOS transistor, abbreviated to a neuMOS, has more than two input gates. It is a highly functional device and has a potential to reduce the number of transistors and the area, compared with CMOS circuits. We propose a module generator which generates 2-level neuMOS circuits for logic functions with small numbers of input variables. Using the module generator, we show 2-level neuMOS circuits for all 3-variable logic functions.
AB - A neuron MOS transistor, abbreviated to a neuMOS, has more than two input gates. It is a highly functional device and has a potential to reduce the number of transistors and the area, compared with CMOS circuits. We propose a module generator which generates 2-level neuMOS circuits for logic functions with small numbers of input variables. Using the module generator, we show 2-level neuMOS circuits for all 3-variable logic functions.
UR - http://www.scopus.com/inward/record.url?scp=0004953522&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0004953522&partnerID=8YFLogxK
U2 - 10.1016/S0045-7906(97)00040-2
DO - 10.1016/S0045-7906(97)00040-2
M3 - Article
AN - SCOPUS:0004953522
VL - 24
SP - 33
EP - 41
JO - Computers and Electrical Engineering
JF - Computers and Electrical Engineering
SN - 0045-7906
IS - 1-2
ER -