A new metal-oxide-silicon (MOS)/bipolar merged transistor structure in a silicon on insulator (SOI), which has a MOS structure with a built-in bipolar mechanism, is proposed. The transistor has a frame of a metal-oxide-silicon field-effect-transistor (MOSFET) having the gate at the bottom. A vertical bipolar transistor is built in the drain region by introducing an opposite-type impurity through a polycrystalline silicon buffer layer. Implementation of the device in an SOI structure avoids parasitic effects such as the latch-up, which appears when a merged structure is used to construct a complementary circuit. A two-dimensional device simulation shows the current amplification property of the merged transistor, while also revealing the critical design parameter for successful operation. A test device is fabricated using a process which employs a wafer bonding and polish-back technique. The results prove the feasibility of the proposed device.
|Number of pages||5|
|Journal||Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers|
|Issue number||4 B|
|Publication status||Published - 1999|
All Science Journal Classification (ASJC) codes
- Physics and Astronomy(all)