Abstract
A new metal-oxide-silicon (MOS)/bipolar merged transistor structure in a silicon on insulator (SOI), which has a MOS structure with a built-in bipolar mechanism, is proposed. The transistor has a frame of a metal-oxide-silicon field-effect-transistor (MOSFET) having the gate at the bottom. A vertical bipolar transistor is built in the drain region by introducing an opposite-type impurity through a polycrystalline silicon buffer layer. Implementation of the device in an SOI structure avoids parasitic effects such as the latch-up, which appears when a merged structure is used to construct a complementary circuit. A two-dimensional device simulation shows the current amplification property of the merged transistor, while also revealing the critical design parameter for successful operation. A test device is fabricated using a process which employs a wafer bonding and polish-back technique. The results prove the feasibility of the proposed device.
| Original language | English |
|---|---|
| Pages (from-to) | 2501-2505 |
| Number of pages | 5 |
| Journal | Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers |
| Volume | 38 |
| Issue number | 4 B |
| Publication status | Published - Dec 1 1999 |
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All Science Journal Classification (ASJC) codes
- Engineering(all)
- Physics and Astronomy(all)
Cite this
A new merged bipolar-MOS transistor in a silicon on insulator structure. / Zheng, Yue Sheng; Asano, Tanemasa.
In: Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, Vol. 38, No. 4 B, 01.12.1999, p. 2501-2505.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - A new merged bipolar-MOS transistor in a silicon on insulator structure
AU - Zheng, Yue Sheng
AU - Asano, Tanemasa
PY - 1999/12/1
Y1 - 1999/12/1
N2 - A new metal-oxide-silicon (MOS)/bipolar merged transistor structure in a silicon on insulator (SOI), which has a MOS structure with a built-in bipolar mechanism, is proposed. The transistor has a frame of a metal-oxide-silicon field-effect-transistor (MOSFET) having the gate at the bottom. A vertical bipolar transistor is built in the drain region by introducing an opposite-type impurity through a polycrystalline silicon buffer layer. Implementation of the device in an SOI structure avoids parasitic effects such as the latch-up, which appears when a merged structure is used to construct a complementary circuit. A two-dimensional device simulation shows the current amplification property of the merged transistor, while also revealing the critical design parameter for successful operation. A test device is fabricated using a process which employs a wafer bonding and polish-back technique. The results prove the feasibility of the proposed device.
AB - A new metal-oxide-silicon (MOS)/bipolar merged transistor structure in a silicon on insulator (SOI), which has a MOS structure with a built-in bipolar mechanism, is proposed. The transistor has a frame of a metal-oxide-silicon field-effect-transistor (MOSFET) having the gate at the bottom. A vertical bipolar transistor is built in the drain region by introducing an opposite-type impurity through a polycrystalline silicon buffer layer. Implementation of the device in an SOI structure avoids parasitic effects such as the latch-up, which appears when a merged structure is used to construct a complementary circuit. A two-dimensional device simulation shows the current amplification property of the merged transistor, while also revealing the critical design parameter for successful operation. A test device is fabricated using a process which employs a wafer bonding and polish-back technique. The results prove the feasibility of the proposed device.
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UR - http://www.scopus.com/inward/citedby.url?scp=0343165352&partnerID=8YFLogxK
M3 - Article
AN - SCOPUS:0343165352
VL - 38
SP - 2501
EP - 2505
JO - Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes
JF - Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes
SN - 0021-4922
IS - 4 B
ER -