A novel capture-safety checking method for multi-clock designs and accuracy evaluation with delay capture circuits

Kohei Miyase, Masao Aso, Ryou Ootsuka, Xiaoqing Wen, Hiroshi Furukawa, Yuta Yamato, Kazunari Enokimoto, Seiji Kajihara

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Excessive capture power in at-speed scan testing may cause yield loss due to timing failures. Although reducing the number of clock domains that capture test responses simultaneously is a practical and scalable solution for reducing capture power, no available capture-safety checking metric can assess its effect in an accurate-enough manner, especially when multiple clock domains capture test responses in a short period of time. This paper proposes a novel CLEAR (CLock-Edge-Arrival-Relation-based) capture-safety checking method that, for the first time, takes clock edge arrival times for different clock domains into consideration. The accuracy and usefulness of the proposed method have been clearly demonstrated by simulation-based evaluation with the largest ITC'99 benchmark circuit as well as real-chip-based evaluation with an industrial chip embedded with on-chip delay measurement circuitry.

Original languageEnglish
Title of host publicationProceedings - 2012 30th IEEE VLSI Test Symposium, VTS 2012
Pages197-202
Number of pages6
DOIs
Publication statusPublished - 2012
Event2012 30th IEEE VLSI Test Symposium, VTS 2012 - Hyatt Maui, HI, United States
Duration: Apr 23 2012Apr 26 2012

Publication series

NameProceedings of the IEEE VLSI Test Symposium

Other

Other2012 30th IEEE VLSI Test Symposium, VTS 2012
CountryUnited States
CityHyatt Maui, HI
Period4/23/124/26/12

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Electrical and Electronic Engineering

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    Miyase, K., Aso, M., Ootsuka, R., Wen, X., Furukawa, H., Yamato, Y., Enokimoto, K., & Kajihara, S. (2012). A novel capture-safety checking method for multi-clock designs and accuracy evaluation with delay capture circuits. In Proceedings - 2012 30th IEEE VLSI Test Symposium, VTS 2012 (pp. 197-202). [6231102] (Proceedings of the IEEE VLSI Test Symposium). https://doi.org/10.1109/VTS.2012.6231102