A novel low on-resistance Schottky-barrier diode with p-buried floating layer structure

Wataru Saito; Ichiro Omura; Ken'ichi Tokano; Tsuneo Ogura; Hiromichi Ohashi

doi:10.1109/TED.2004.826886

A novel low on-resistance Schottky-barrier diode with p-buried floating layer structure

Wataru Saito, Ichiro Omura, Ken'ichi Tokano, Tsuneo Ogura, Hiromichi Ohashi

Research output: Contribution to journal › Article › peer-review

24 Citations (Scopus)

Abstract

A novel low on-resistance Schottky-barrier diode (SBD) structure with a p-buried floating layer is demonstrated by fabricating 300-V SBDs using a buried epitaxial growth technique. The fabricated SBDs realize a 50% reduction of chip area and show a possibility of higher breakdown voltage SBD of over 100 V. In addition, both the low on-resistance and the soft-recovery characteristics can be realized by the p-buried floating layer structure. The demonstrated structure is very attractive for reduction of power dissipation without electromagnetic interference noise increase.

Original language	English
Pages (from-to)	797-802
Number of pages	6
Journal	IEEE Transactions on Electron Devices
Volume	51
Issue number	5
DOIs	https://doi.org/10.1109/TED.2004.826886
Publication status	Published - May 1 2004
Externally published	Yes

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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10.1109/TED.2004.826886

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title = "A novel low on-resistance Schottky-barrier diode with p-buried floating layer structure",

abstract = "A novel low on-resistance Schottky-barrier diode (SBD) structure with a p-buried floating layer is demonstrated by fabricating 300-V SBDs using a buried epitaxial growth technique. The fabricated SBDs realize a 50% reduction of chip area and show a possibility of higher breakdown voltage SBD of over 100 V. In addition, both the low on-resistance and the soft-recovery characteristics can be realized by the p-buried floating layer structure. The demonstrated structure is very attractive for reduction of power dissipation without electromagnetic interference noise increase.",

author = "Wataru Saito and Ichiro Omura and Ken'ichi Tokano and Tsuneo Ogura and Hiromichi Ohashi",

year = "2004",

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T1 - A novel low on-resistance Schottky-barrier diode with p-buried floating layer structure

AU - Saito, Wataru

AU - Omura, Ichiro

AU - Tokano, Ken'ichi

AU - Ogura, Tsuneo

AU - Ohashi, Hiromichi

PY - 2004/5/1

Y1 - 2004/5/1

N2 - A novel low on-resistance Schottky-barrier diode (SBD) structure with a p-buried floating layer is demonstrated by fabricating 300-V SBDs using a buried epitaxial growth technique. The fabricated SBDs realize a 50% reduction of chip area and show a possibility of higher breakdown voltage SBD of over 100 V. In addition, both the low on-resistance and the soft-recovery characteristics can be realized by the p-buried floating layer structure. The demonstrated structure is very attractive for reduction of power dissipation without electromagnetic interference noise increase.

AB - A novel low on-resistance Schottky-barrier diode (SBD) structure with a p-buried floating layer is demonstrated by fabricating 300-V SBDs using a buried epitaxial growth technique. The fabricated SBDs realize a 50% reduction of chip area and show a possibility of higher breakdown voltage SBD of over 100 V. In addition, both the low on-resistance and the soft-recovery characteristics can be realized by the p-buried floating layer structure. The demonstrated structure is very attractive for reduction of power dissipation without electromagnetic interference noise increase.

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JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

SN - 0018-9383

IS - 5

ER -

A novel low on-resistance Schottky-barrier diode with p-buried floating layer structure

Abstract

All Science Journal Classification (ASJC) codes

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