Abstract
A novel low on-resistance Schottky-barrier diode (SBD) structure with a p-buried floating layer is demonstrated by fabricating 300-V SBDs using a buried epitaxial growth technique. The fabricated SBDs realize a 50% reduction of chip area and show a possibility of higher breakdown voltage SBD of over 100 V. In addition, both the low on-resistance and the soft-recovery characteristics can be realized by the p-buried floating layer structure. The demonstrated structure is very attractive for reduction of power dissipation without electromagnetic interference noise increase.
| Original language | English |
|---|---|
| Pages (from-to) | 797-802 |
| Number of pages | 6 |
| Journal | IEEE Transactions on Electron Devices |
| Volume | 51 |
| Issue number | 5 |
| DOIs | |
| Publication status | Published - May 1 2004 |
| Externally published | Yes |
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering
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Cite this
Saito, W., Omura, I., Tokano, K., Ogura, T., & Ohashi, H. (2004). A novel low on-resistance Schottky-barrier diode with p-buried floating layer structure. IEEE Transactions on Electron Devices, 51(5), 797-802. https://doi.org/10.1109/TED.2004.826886